// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  cpi_reg_offset.h
// Project line  :  IT产品线
// Department    :  图灵ICT处理器开发部
// Author        :  xxx
// Version       :  V100
// Date          :
// Description   :  Hi 1823 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability
// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and
// CT product. Others        :  Generated automatically by nManager V5.1 History       :  xxx 2020/07/27 20:37:29 Create
// file
// ******************************************************************************

#ifndef CPI_REG_OFFSET_H
#define CPI_REG_OFFSET_H

/* msi_cap_csr Base address of Module's Register */
#define CSR_MSI_CAP_CSR_BASE (0x43F9000)

/* **************************************************************************** */
/*                      msi_cap_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_MSI_CAP_CSR_MSI_CAP_CSR_DW0_0_REG (CSR_MSI_CAP_CSR_BASE + 0x0)
#define CSR_MSI_CAP_CSR_MSI_CAP_CSR_DW0_1_REG (CSR_MSI_CAP_CSR_BASE + 0x4)

/* up_itf_csr Base address of Module's Register */
#define CSR_UP_ITF_CSR_BASE (0x43AE000)

/* **************************************************************************** */
/*                      up_itf_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_UP_ITF_CSR_UP_PCIE_STATUS_REG (CSR_UP_ITF_CSR_BASE + 0x0)        /* PCIe端口link实时状态。 */
#define CSR_UP_ITF_CSR_UP_INT_STATUS_REG (CSR_UP_ITF_CSR_BASE + 0x4)         /* 中断状态寄存器；写1清除对应比特中断。 */
#define CSR_UP_ITF_CSR_UP_INT_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x8)            /* uP interrupt control */
#define CSR_UP_ITF_CSR_UP_DIRECT_ACCESS_LOCK_REG (CSR_UP_ITF_CSR_BASE + 0xC) /* direct access lock */
#define CSR_UP_ITF_CSR_UP_AEQ_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x10)           /* uP AEQ length and AEQE size */
#define CSR_UP_ITF_CSR_UP_AEQ_BA_REG (CSR_UP_ITF_CSR_BASE + 0x14)            /* uP AEQ ring buffer base address */
#define CSR_UP_ITF_CSR_UP_AEQ_CI_REG (CSR_UP_ITF_CSR_BASE + 0x18)            /* uP AEQ ring buffer CI */
#define CSR_UP_ITF_CSR_UP_AEQ_PI_REG (CSR_UP_ITF_CSR_BASE + 0x1C)            /* uP AEQ ring buffer PI */
#define CSR_UP_ITF_CSR_UP_RX_API_BUF_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x20)    /* uP API Rx ring buffer length */
#define CSR_UP_ITF_CSR_UP_RX_API_BUF_BA_REG (CSR_UP_ITF_CSR_BASE + 0x24)     /* uP API Rx ring buffer base address */
#define CSR_UP_ITF_CSR_UP_RX_API_BUF_CI_REG (CSR_UP_ITF_CSR_BASE + 0x28)     /* uP API Rx ring buffer CI */
#define CSR_UP_ITF_CSR_UP_RX_API_BUF_PI_REG (CSR_UP_ITF_CSR_BASE + 0x2C)     /* uP API Rx ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TX_API_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x30)        /* uP API Tx control register */
#define CSR_UP_ITF_CSR_UP_TX_API_CTL_VIO_REG (CSR_UP_ITF_CSR_BASE + 0x34) /* mpu tx api ctrl register for VirtIO/NVMe \
                                                                           */
#define CSR_UP_ITF_CSR_UP_RB_TIMEOUT_REG (CSR_UP_ITF_CSR_BASE + 0x38)     /* UP RINGBuffer申请时间约束。 */
#define CSR_UP_ITF_CSR_UP_XFER_CTRL_REG (CSR_UP_ITF_CSR_BASE + 0x3C)      /* UP AXI接口控制寄存器 */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_0_REG (CSR_UP_ITF_CSR_BASE + 0x40)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_1_REG (CSR_UP_ITF_CSR_BASE + 0x44)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_2_REG (CSR_UP_ITF_CSR_BASE + 0x48)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_3_REG (CSR_UP_ITF_CSR_BASE + 0x4C)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_4_REG (CSR_UP_ITF_CSR_BASE + 0x50)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_5_REG (CSR_UP_ITF_CSR_BASE + 0x54)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_6_REG (CSR_UP_ITF_CSR_BASE + 0x58)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_7_REG (CSR_UP_ITF_CSR_BASE + 0x5C)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_8_REG (CSR_UP_ITF_CSR_BASE + 0x60)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_9_REG (CSR_UP_ITF_CSR_BASE + 0x64)  /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_10_REG (CSR_UP_ITF_CSR_BASE + 0x68) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_11_REG (CSR_UP_ITF_CSR_BASE + 0x6C) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_12_REG (CSR_UP_ITF_CSR_BASE + 0x70) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_13_REG (CSR_UP_ITF_CSR_BASE + 0x74) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_14_REG (CSR_UP_ITF_CSR_BASE + 0x78) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_15_REG (CSR_UP_ITF_CSR_BASE + 0x7C) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_16_REG (CSR_UP_ITF_CSR_BASE + 0x80) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_17_REG (CSR_UP_ITF_CSR_BASE + 0x84) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_18_REG (CSR_UP_ITF_CSR_BASE + 0x88) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_19_REG (CSR_UP_ITF_CSR_BASE + 0x8C) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_20_REG (CSR_UP_ITF_CSR_BASE + 0x90) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_21_REG (CSR_UP_ITF_CSR_BASE + 0x94) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_22_REG (CSR_UP_ITF_CSR_BASE + 0x98) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_23_REG (CSR_UP_ITF_CSR_BASE + 0x9C) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_24_REG (CSR_UP_ITF_CSR_BASE + 0xA0) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_25_REG (CSR_UP_ITF_CSR_BASE + 0xA4) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_26_REG (CSR_UP_ITF_CSR_BASE + 0xA8) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_27_REG (CSR_UP_ITF_CSR_BASE + 0xAC) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_28_REG (CSR_UP_ITF_CSR_BASE + 0xB0) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_29_REG (CSR_UP_ITF_CSR_BASE + 0xB4) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_30_REG (CSR_UP_ITF_CSR_BASE + 0xB8) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_31_REG (CSR_UP_ITF_CSR_BASE + 0xBC) /* the payload data of the uP Tx API */
#define CSR_UP_ITF_CSR_UP_INT_COLL_REG (CSR_UP_ITF_CSR_BASE + 0xC8)          /* uP interrupt collection. */
#define CSR_UP_ITF_CSR_UP_INT_TIMEOUT_REG (CSR_UP_ITF_CSR_BASE + 0xCC)       /* uP interrupt collection timeout. */
#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_0_REG (CSR_UP_ITF_CSR_BASE + 0xD0)      /* uP TLP Rx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_1_REG (CSR_UP_ITF_CSR_BASE + 0xF0)      /* uP TLP Rx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_2_REG (CSR_UP_ITF_CSR_BASE + 0x110)     /* uP TLP Rx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_3_REG (CSR_UP_ITF_CSR_BASE + 0x130)     /* uP TLP Rx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_0_REG (CSR_UP_ITF_CSR_BASE + 0xD4)       /* uP TLP ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_1_REG (CSR_UP_ITF_CSR_BASE + 0xF4)       /* uP TLP ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_2_REG (CSR_UP_ITF_CSR_BASE + 0x114)      /* uP TLP ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_3_REG (CSR_UP_ITF_CSR_BASE + 0x134)      /* uP TLP ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_0_REG (CSR_UP_ITF_CSR_BASE + 0xD8)       /* uP TLP ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_1_REG (CSR_UP_ITF_CSR_BASE + 0xF8)       /* uP TLP ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_2_REG (CSR_UP_ITF_CSR_BASE + 0x118)      /* uP TLP ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_3_REG (CSR_UP_ITF_CSR_BASE + 0x138)      /* uP TLP ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_0_REG (CSR_UP_ITF_CSR_BASE + 0xDC)       /* uP TLP ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_1_REG (CSR_UP_ITF_CSR_BASE + 0xFC)       /* uP TLP ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_2_REG (CSR_UP_ITF_CSR_BASE + 0x11C)      /* uP TLP ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_3_REG (CSR_UP_ITF_CSR_BASE + 0x13C)      /* uP TLP ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_0_REG (CSR_UP_ITF_CSR_BASE + 0xE0)      /* uP TLP Tx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_1_REG (CSR_UP_ITF_CSR_BASE + 0x100)     /* uP TLP Tx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_2_REG (CSR_UP_ITF_CSR_BASE + 0x120)     /* uP TLP Tx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_3_REG (CSR_UP_ITF_CSR_BASE + 0x140)     /* uP TLP Tx ring buffer length */
#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_0_REG (CSR_UP_ITF_CSR_BASE + 0xE4)       /* uP TLP TX ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_1_REG (CSR_UP_ITF_CSR_BASE + 0x104)      /* uP TLP TX ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_2_REG (CSR_UP_ITF_CSR_BASE + 0x124)      /* uP TLP TX ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_3_REG (CSR_UP_ITF_CSR_BASE + 0x144)      /* uP TLP TX ring buffer base address */
#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_0_REG (CSR_UP_ITF_CSR_BASE + 0xE8)       /* uP TLP Tx ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_1_REG (CSR_UP_ITF_CSR_BASE + 0x108)      /* uP TLP Tx ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_2_REG (CSR_UP_ITF_CSR_BASE + 0x128)      /* uP TLP Tx ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_3_REG (CSR_UP_ITF_CSR_BASE + 0x148)      /* uP TLP Tx ring buffer CI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_0_REG (CSR_UP_ITF_CSR_BASE + 0xEC)       /* uP TLP Tx ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_1_REG (CSR_UP_ITF_CSR_BASE + 0x10C)      /* uP TLP Tx ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_2_REG (CSR_UP_ITF_CSR_BASE + 0x12C)      /* uP TLP Tx ring buffer PI */
#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_3_REG (CSR_UP_ITF_CSR_BASE + 0x14C)      /* uP TLP Tx ring buffer PI */
#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x150) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x170) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x190) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1B0) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x154) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x174) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x194) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1B4) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x158) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x178) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x198) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1B8) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x15C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x17C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x19C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1BC) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x160) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x180) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1A0) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1C0) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x164) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x184) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1A4) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1C4) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x168) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x188) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1A8) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1C8) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_0_REG \
    (CSR_UP_ITF_CSR_BASE + 0x16C) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_1_REG \
    (CSR_UP_ITF_CSR_BASE + 0x18C) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_2_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1AC) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_3_REG \
    (CSR_UP_ITF_CSR_BASE + 0x1CC)                                     /* uP MCTP Tx ring buffer PI for port[pcie_idx] */
#define CSR_UP_ITF_CSR_UP_CSR_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x200)   /* UP访问系统CSR寄存器的控制寄存器 */
#define CSR_UP_ITF_CSR_UP_CSR_DATA0_REG (CSR_UP_ITF_CSR_BASE + 0x204) /* UP访问CSR的数据寄存器0 */
#define CSR_UP_ITF_CSR_UP_CSR_DATA1_REG (CSR_UP_ITF_CSR_BASE + 0x208) /* UP访问CSR的数据寄存器1 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_0_REG (CSR_UP_ITF_CSR_BASE + 0x300)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_1_REG (CSR_UP_ITF_CSR_BASE + 0x304)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_2_REG (CSR_UP_ITF_CSR_BASE + 0x308)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_3_REG (CSR_UP_ITF_CSR_BASE + 0x30C)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_4_REG (CSR_UP_ITF_CSR_BASE + 0x310)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_5_REG (CSR_UP_ITF_CSR_BASE + 0x314)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_6_REG (CSR_UP_ITF_CSR_BASE + 0x318)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_7_REG (CSR_UP_ITF_CSR_BASE + 0x31C)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_8_REG (CSR_UP_ITF_CSR_BASE + 0x320)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_9_REG (CSR_UP_ITF_CSR_BASE + 0x324)  /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_10_REG (CSR_UP_ITF_CSR_BASE + 0x328) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_11_REG (CSR_UP_ITF_CSR_BASE + 0x32C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_12_REG (CSR_UP_ITF_CSR_BASE + 0x330) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_13_REG (CSR_UP_ITF_CSR_BASE + 0x334) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_14_REG (CSR_UP_ITF_CSR_BASE + 0x338) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_15_REG (CSR_UP_ITF_CSR_BASE + 0x33C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_16_REG (CSR_UP_ITF_CSR_BASE + 0x340) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_17_REG (CSR_UP_ITF_CSR_BASE + 0x344) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_18_REG (CSR_UP_ITF_CSR_BASE + 0x348) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_19_REG (CSR_UP_ITF_CSR_BASE + 0x34C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_20_REG (CSR_UP_ITF_CSR_BASE + 0x350) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_21_REG (CSR_UP_ITF_CSR_BASE + 0x354) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_22_REG (CSR_UP_ITF_CSR_BASE + 0x358) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_23_REG (CSR_UP_ITF_CSR_BASE + 0x35C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_24_REG (CSR_UP_ITF_CSR_BASE + 0x360) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_25_REG (CSR_UP_ITF_CSR_BASE + 0x364) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_26_REG (CSR_UP_ITF_CSR_BASE + 0x368) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_27_REG (CSR_UP_ITF_CSR_BASE + 0x36C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_28_REG (CSR_UP_ITF_CSR_BASE + 0x370) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_29_REG (CSR_UP_ITF_CSR_BASE + 0x374) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_30_REG (CSR_UP_ITF_CSR_BASE + 0x378) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_31_REG (CSR_UP_ITF_CSR_BASE + 0x37C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_32_REG (CSR_UP_ITF_CSR_BASE + 0x380) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_33_REG (CSR_UP_ITF_CSR_BASE + 0x384) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_34_REG (CSR_UP_ITF_CSR_BASE + 0x388) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_35_REG (CSR_UP_ITF_CSR_BASE + 0x38C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_36_REG (CSR_UP_ITF_CSR_BASE + 0x390) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_37_REG (CSR_UP_ITF_CSR_BASE + 0x394) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_38_REG (CSR_UP_ITF_CSR_BASE + 0x398) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_39_REG (CSR_UP_ITF_CSR_BASE + 0x39C) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_40_REG (CSR_UP_ITF_CSR_BASE + 0x3A0) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_41_REG (CSR_UP_ITF_CSR_BASE + 0x3A4) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_42_REG (CSR_UP_ITF_CSR_BASE + 0x3A8) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_43_REG (CSR_UP_ITF_CSR_BASE + 0x3AC) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_44_REG (CSR_UP_ITF_CSR_BASE + 0x3B0) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_45_REG (CSR_UP_ITF_CSR_BASE + 0x3B4) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_46_REG (CSR_UP_ITF_CSR_BASE + 0x3B8) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_47_REG (CSR_UP_ITF_CSR_BASE + 0x3BC) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_48_REG (CSR_UP_ITF_CSR_BASE + 0x3C0) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_49_REG (CSR_UP_ITF_CSR_BASE + 0x3C4) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_50_REG (CSR_UP_ITF_CSR_BASE + 0x3C8) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_51_REG (CSR_UP_ITF_CSR_BASE + 0x3CC) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_52_REG (CSR_UP_ITF_CSR_BASE + 0x3D0) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_53_REG (CSR_UP_ITF_CSR_BASE + 0x3D4) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_54_REG (CSR_UP_ITF_CSR_BASE + 0x3D8) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_55_REG (CSR_UP_ITF_CSR_BASE + 0x3DC) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_56_REG (CSR_UP_ITF_CSR_BASE + 0x3E0) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_57_REG (CSR_UP_ITF_CSR_BASE + 0x3E4) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_58_REG (CSR_UP_ITF_CSR_BASE + 0x3E8) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_59_REG (CSR_UP_ITF_CSR_BASE + 0x3EC) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_60_REG (CSR_UP_ITF_CSR_BASE + 0x3F0) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_61_REG (CSR_UP_ITF_CSR_BASE + 0x3F4) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_62_REG (CSR_UP_ITF_CSR_BASE + 0x3F8) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_API_RDAT_63_REG (CSR_UP_ITF_CSR_BASE + 0x3FC) /* UP API Load访问的读数据 */
#define CSR_UP_ITF_CSR_UP_MEM_CTRL_REG (CSR_UP_ITF_CSR_BASE + 0x400)    /* 接口Memory属性配置寄存器。保持为默认值。 */
#define CSR_UP_ITF_CSR_UP_RB_DBGCTL_REG (CSR_UP_ITF_CSR_BASE + 0x404)   /* UP RingBuffer Debug控制寄存器 */
#define CSR_UP_ITF_CSR_UP_RB_DBGDAT0_REG (CSR_UP_ITF_CSR_BASE + 0x408)  /* RingBuffer指针状态。 */
#define CSR_UP_ITF_CSR_UP_RB_DBGDAT1_REG (CSR_UP_ITF_CSR_BASE + 0x40C)  /* RingBuffer数据个数状态。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG0_REG (CSR_UP_ITF_CSR_BASE + 0x410)    /* 内部状态0。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG1_REG (CSR_UP_ITF_CSR_BASE + 0x414)    /* 内部状态1。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG2_REG (CSR_UP_ITF_CSR_BASE + 0x418)    /* 内部状态2。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG3_0_REG (CSR_UP_ITF_CSR_BASE + 0x420)  /* 内部状态3。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG3_1_REG (CSR_UP_ITF_CSR_BASE + 0x424)  /* 内部状态3。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG3_2_REG (CSR_UP_ITF_CSR_BASE + 0x428)  /* 内部状态3。 */
#define CSR_UP_ITF_CSR_UP_FSM_DBG3_3_REG (CSR_UP_ITF_CSR_BASE + 0x42C)  /* 内部状态3。 */
#define CSR_UP_ITF_CSR_UP_MEM_DBG0_REG (CSR_UP_ITF_CSR_BASE + 0x430)    /* Memory错误注入寄存器 */
#define CSR_UP_ITF_CSR_UP_MEM_DBG1_REG (CSR_UP_ITF_CSR_BASE + 0x434)    /* MEM错误状态寄存器1 */
#define CSR_UP_ITF_CSR_UP_MEM_DBG2_REG (CSR_UP_ITF_CSR_BASE + 0x438)    /* MEM错误状态寄存器2 */
#define CSR_UP_ITF_CSR_UP_MEM_DBG3_REG (CSR_UP_ITF_CSR_BASE + 0x43C)    /* MEM错误状态寄存器3 */
#define CSR_UP_ITF_CSR_UP_DBG_ST0_REG (CSR_UP_ITF_CSR_BASE + 0x440)     /* DFX状态寄存器0 */
#define CSR_UP_ITF_CSR_UP_DBG_ST1_REG (CSR_UP_ITF_CSR_BASE + 0x444)     /* DFX状态寄存器1 */
#define CSR_UP_ITF_CSR_UP_DBG_ST2_REG (CSR_UP_ITF_CSR_BASE + 0x448)     /* DFX状态寄存器2 */
#define CSR_UP_ITF_CSR_UP_DBG_ST3_REG (CSR_UP_ITF_CSR_BASE + 0x44C)     /* DFX状态寄存器3 */
#define CSR_UP_ITF_CSR_UP_MEM_DBG4_REG (CSR_UP_ITF_CSR_BASE + 0x450)    /* MEM错误状态寄存器4 */
#define CSR_UP_ITF_CSR_UP_DBG_CNT0_REG (CSR_UP_ITF_CSR_BASE + 0x460)    /* DFX统计寄存器0 */
#define CSR_UP_ITF_CSR_UP_DBG_CNT1_REG (CSR_UP_ITF_CSR_BASE + 0x464)
#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x470) /* uP MB Rx ring buffer length */
#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_BA_REG (CSR_UP_ITF_CSR_BASE + 0x474)  /* uP MB Rx ring buffer base address */
#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_CI_REG (CSR_UP_ITF_CSR_BASE + 0x478)  /* uP MB Rx ring buffer CI */
#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_PI_REG (CSR_UP_ITF_CSR_BASE + 0x47C)  /* uP MB Rx ring buffer PI */
#define CSR_UP_ITF_CSR_UP_BAR_MAP_REG (CSR_UP_ITF_CSR_BASE + 0x480)       /* CPI BAR空间映射 */
#define CSR_UP_ITF_CSR_UP_ACC_FUNC_IDX_REG (CSR_UP_ITF_CSR_BASE + 0x484)
#define CSR_UP_ITF_CSR_UP_INT_STATUS2_REG (CSR_UP_ITF_CSR_BASE + 0x490)      /* 中断状态寄存器；写1清除对应比特中断。 */
#define CSR_UP_ITF_CSR_UP_INT_CTL2_REG (CSR_UP_ITF_CSR_BASE + 0x494)         /* uP interrupt control */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_TH_REG (CSR_UP_ITF_CSR_BASE + 0x4A0)    /* 并发度门限 */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_CNT_REG (CSR_UP_ITF_CSR_BASE + 0x4A4)   /* 并发数统计 */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_REC_REG (CSR_UP_ITF_CSR_BASE + 0x4A8)   /* 并发数恢复 */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD0_REG (CSR_UP_ITF_CSR_BASE + 0x4B0) /* 丢弃情况记录 */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD1_REG (CSR_UP_ITF_CSR_BASE + 0x4B4) /* 丢弃情况记录 */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD2_REG (CSR_UP_ITF_CSR_BASE + 0x4B8) /* 丢弃情况记录 */
#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD3_REG (CSR_UP_ITF_CSR_BASE + 0x4BC) /* 丢弃情况记录 */
#define CSR_UP_ITF_CSR_UP_UNCRT_ERR_DIS_REG (CSR_UP_ITF_CSR_BASE + 0x4C0)

/* func_com_csr Base address of Module's Register */
#define CSR_FUNC_COM_CSR_BASE (0x4000000)

/* **************************************************************************** */
/*                      func_com_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE0_0_REG (CSR_FUNC_COM_CSR_BASE + 0x0)  /* Function attribute0 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE0_1_REG (CSR_FUNC_COM_CSR_BASE + 0x80) /* Function attribute0 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE1_0_REG (CSR_FUNC_COM_CSR_BASE + 0x4)  /* Function attribute1 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE1_1_REG (CSR_FUNC_COM_CSR_BASE + 0x84) /* Function attribute1 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE2_0_REG (CSR_FUNC_COM_CSR_BASE + 0x8)  /* function attribute2 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE2_1_REG (CSR_FUNC_COM_CSR_BASE + 0x88) /* function attribute2 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE3_0_REG (CSR_FUNC_COM_CSR_BASE + 0xC)  /* Function attribute3 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE3_1_REG (CSR_FUNC_COM_CSR_BASE + 0x8C) /* Function attribute3 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE4_0_REG (CSR_FUNC_COM_CSR_BASE + 0x10) /* Function attribute4 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE4_1_REG (CSR_FUNC_COM_CSR_BASE + 0x90) /* Function attribute4 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE5_0_REG (CSR_FUNC_COM_CSR_BASE + 0x14) /* Function attribute5 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE5_1_REG (CSR_FUNC_COM_CSR_BASE + 0x94) /* Function attribute5 */
#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE6_0_REG (CSR_FUNC_COM_CSR_BASE + 0x18) /* Function attribute6 */

#define CSR_FUNC_COM_CSR_FUNCTION_TSK0_0_REG (CSR_FUNC_COM_CSR_BASE + 0x20)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_0_REG (CSR_FUNC_COM_CSR_BASE + 0x24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_1_REG (CSR_FUNC_COM_CSR_BASE + 0xA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_2_REG (CSR_FUNC_COM_CSR_BASE + 0x124)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_4_REG (CSR_FUNC_COM_CSR_BASE + 0x224)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_6_REG (CSR_FUNC_COM_CSR_BASE + 0x324)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_8_REG (CSR_FUNC_COM_CSR_BASE + 0x424)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_10_REG (CSR_FUNC_COM_CSR_BASE + 0x524)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_12_REG (CSR_FUNC_COM_CSR_BASE + 0x624)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_14_REG (CSR_FUNC_COM_CSR_BASE + 0x724)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_16_REG (CSR_FUNC_COM_CSR_BASE + 0x824)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_18_REG (CSR_FUNC_COM_CSR_BASE + 0x924)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9A4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF24)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFA4)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_0_REG (CSR_FUNC_COM_CSR_BASE + 0x28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_1_REG (CSR_FUNC_COM_CSR_BASE + 0xA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_2_REG (CSR_FUNC_COM_CSR_BASE + 0x128)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_4_REG (CSR_FUNC_COM_CSR_BASE + 0x228)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_6_REG (CSR_FUNC_COM_CSR_BASE + 0x328)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_8_REG (CSR_FUNC_COM_CSR_BASE + 0x428)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_10_REG (CSR_FUNC_COM_CSR_BASE + 0x528)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_12_REG (CSR_FUNC_COM_CSR_BASE + 0x628)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_14_REG (CSR_FUNC_COM_CSR_BASE + 0x728)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_16_REG (CSR_FUNC_COM_CSR_BASE + 0x828)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_18_REG (CSR_FUNC_COM_CSR_BASE + 0x928)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9A8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF28)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFA8)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_0_REG (CSR_FUNC_COM_CSR_BASE + 0x2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_1_REG (CSR_FUNC_COM_CSR_BASE + 0xAC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_2_REG (CSR_FUNC_COM_CSR_BASE + 0x12C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_4_REG (CSR_FUNC_COM_CSR_BASE + 0x22C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_6_REG (CSR_FUNC_COM_CSR_BASE + 0x32C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_8_REG (CSR_FUNC_COM_CSR_BASE + 0x42C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_10_REG (CSR_FUNC_COM_CSR_BASE + 0x52C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_12_REG (CSR_FUNC_COM_CSR_BASE + 0x62C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_14_REG (CSR_FUNC_COM_CSR_BASE + 0x72C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_16_REG (CSR_FUNC_COM_CSR_BASE + 0x82C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_18_REG (CSR_FUNC_COM_CSR_BASE + 0x92C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9AC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAAC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBAC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCAC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDAC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEAC)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF2C)
#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFAC)
#define CSR_FUNC_COM_CSR_FUNC_REMAP_TABLE_ENTR_0_REG (CSR_FUNC_COM_CSR_BASE + 0x30) /* function remap table entry */
#define CSR_FUNC_COM_CSR_FUNC_REMAP_TABLE_ENTR_1_REG (CSR_FUNC_COM_CSR_BASE + 0xB0) /* function remap table entry */
#define CSR_FUNC_COM_CSR_FUNC_AEQ_CI_INDIR_WR_REG \
    (CSR_FUNC_COM_CSR_BASE + 0x50) /* AEQ CI simple indirect access path */
#define CSR_FUNC_COM_CSR_FUNC_CEQ_CI_INDIR_WR_REG \
    (CSR_FUNC_COM_CSR_BASE + 0x54) /* CEQ CI simple indirect access path */
#define CSR_FUNC_COM_CSR_FUNC_MSI_CLR_INDIR_WR_REG \
    (CSR_FUNC_COM_CSR_BASE + 0x58) /* MSI_CTL CLR simple indirect access path */
#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT0_REG (CSR_FUNC_COM_CSR_BASE + 0x60) /* ppf election results in port0 */
#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT1_REG (CSR_FUNC_COM_CSR_BASE + 0x64) /* ppf election results in port1 */
#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT2_REG (CSR_FUNC_COM_CSR_BASE + 0x68) /* ppf election results in port2 */
#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT3_REG (CSR_FUNC_COM_CSR_BASE + 0x6C) /* ppf election results in port3 */
#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT4_REG (CSR_FUNC_COM_CSR_BASE + 0x70) /* ppf election results in port4 */

/* func_mb_dat_csr Base address of Module's Register */
#define CSR_FUNC_MB_DAT_CSR_BASE (0x4080000)

/* **************************************************************************** */
/*                      func_mb_dat_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_0_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x0)   /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_0_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x80)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_1_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x4)   /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_1_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x84)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_2_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x8)   /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_2_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x88)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_3_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xC)   /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_3_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x8C)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_4_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x10)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_4_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x90)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_5_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x14)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_5_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x94)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_6_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x18)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_6_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x98)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_7_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x1C)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_7_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x9C)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_8_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x20)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_8_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA0)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_9_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x24)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_9_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA4)  /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_10_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x28) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_10_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA8) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_11_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x2C) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_11_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xAC) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_12_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x30) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_12_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB0) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_13_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x34) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_13_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB4) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_14_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x38) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_14_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB8) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_15_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x3C) /* mailbox data */
#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_15_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xBC) /* mailbox data */

/* func_mb_csr Base address of Module's Register */
#define CSR_FUNC_MB_CSR_BASE (0x4100000)

/* **************************************************************************** */
/*                      func_mb_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_FUNC_MB_CSR_MAILBOX_CONTROL_0_REG (CSR_FUNC_MB_CSR_BASE + 0x0)     /* Maibox control */
#define CSR_FUNC_MB_CSR_MAILBOX_CONTROL_1_REG (CSR_FUNC_MB_CSR_BASE + 0x80)    /* Maibox control */
#define CSR_FUNC_MB_CSR_MAILBOX_INT_OFFSET_0_REG (CSR_FUNC_MB_CSR_BASE + 0x4)  /* Mailbox interrupt offset */
#define CSR_FUNC_MB_CSR_MAILBOX_INT_OFFSET_1_REG (CSR_FUNC_MB_CSR_BASE + 0x84) /* Mailbox interrupt offset */
#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_H_0_REG \
    (CSR_FUNC_MB_CSR_BASE + 0x8) /* Maibox data sending result back address high 32 bits */
#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_H_1_REG \
    (CSR_FUNC_MB_CSR_BASE + 0x88) /* Maibox data sending result back address high 32 bits */
#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_L_0_REG \
    (CSR_FUNC_MB_CSR_BASE + 0xC) /* Maibox data sending result back address low 32 bits */
#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_L_1_REG \
    (CSR_FUNC_MB_CSR_BASE + 0x8C) /* Maibox data sending result back address low 32 bits */

/* func_aeq_csr Base address of Module's Register */
#define CSR_FUNC_AEQ_CSR_BASE (0x4181000)

/* **************************************************************************** */
/*                      func_aeq_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_FUNC_AEQ_CSR_AEQ_CTL_0_0_REG                                                                          \
    (CSR_FUNC_AEQ_CSR_BASE + 0x0) /* Each PF use offset = 0x200 to access this csr after correct configuration of \
                                     AEQ_INDIR_IDX.VF offset = 0x2200. */
#define CSR_FUNC_AEQ_CSR_AEQ_CTL_0_1_REG                                                                           \
    (CSR_FUNC_AEQ_CSR_BASE + 0x80) /* Each PF use offset = 0x200 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2200. */
#define CSR_FUNC_AEQ_CSR_AEQ_CTL_1_0_REG                                                                          \
    (CSR_FUNC_AEQ_CSR_BASE + 0x4) /* Each PF use offset = 0x204 to access this csr after correct configuration of \
                                     AEQ_INDIR_IDX.VF offset = 0x2204. */
#define CSR_FUNC_AEQ_CSR_AEQ_CTL_1_1_REG                                                                           \
    (CSR_FUNC_AEQ_CSR_BASE + 0x84) /* Each PF use offset = 0x204 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2204. */
#define CSR_FUNC_AEQ_CSR_AEQ_CI_0_REG                                                                             \
    (CSR_FUNC_AEQ_CSR_BASE + 0x8) /* Each PF use offset = 0x208 to access this csr after correct configuration of \
                                     AEQ_INDIR_IDX.VF offset = 0x2208. */
#define CSR_FUNC_AEQ_CSR_AEQ_CI_1_REG                                                                              \
    (CSR_FUNC_AEQ_CSR_BASE + 0x88) /* Each PF use offset = 0x208 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2208. */
#define CSR_FUNC_AEQ_CSR_AEQ_PI_0_REG                                                                             \
    (CSR_FUNC_AEQ_CSR_BASE + 0xC) /* Each PF use offset = 0x20C to access this csr after correct configuration of \
                                     AEQ_INDIR_IDX.VF offset = 0x220C. */
#define CSR_FUNC_AEQ_CSR_AEQ_PI_1_REG                                                                              \
    (CSR_FUNC_AEQ_CSR_BASE + 0x8C) /* Each PF use offset = 0x20C to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x220C. */
#define CSR_FUNC_AEQ_CSR_AEQ_INDIR_IDX_0_REG \
    (CSR_FUNC_AEQ_CSR_BASE +                 \
        0x10) /* Each PF use offset = 0x210 to access this csr. VF offset = 0x2210.MPU cann't access this CSR. */
#define CSR_FUNC_AEQ_CSR_AEQ_INDIR_IDX_1_REG \
    (CSR_FUNC_AEQ_CSR_BASE +                 \
        0x90) /* Each PF use offset = 0x210 to access this csr. VF offset = 0x2210.MPU cann't access this CSR. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_H_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x40) /* Each PF use offset = 0x240 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2240. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_H_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xC0) /* Each PF use offset = 0x240 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2240. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_L_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x44) /* Each PF use offset = 0x244 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2244. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_L_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xC4) /* Each PF use offset = 0x244 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2244. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_H_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x48) /* Each PF use offset = 0x248 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2248. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_H_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xC8) /* Each PF use offset = 0x248 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2248. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_L_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x4C) /* Each PF use offset = 0x24C to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x224C. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_L_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xCC) /* Each PF use offset = 0x24C to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x224C. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_H_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x50) /* Each PF use offset = 0x250 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2250. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_H_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xD0) /* Each PF use offset = 0x250 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2250. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_L_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x54) /* Each PF use offset = 0x254 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2254. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_L_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xD4) /* Each PF use offset = 0x254 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2254. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_H_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x58) /* Each PF use offset = 0x258 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2258. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_H_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xD8) /* Each PF use offset = 0x258 to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x2258. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_L_0_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0x5C) /* Each PF use offset = 0x25C to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x225C. */
#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_L_1_REG                                                                 \
    (CSR_FUNC_AEQ_CSR_BASE + 0xDC) /* Each PF use offset = 0x25C to access this csr after correct configuration of \
                                      AEQ_INDIR_IDX.VF offset = 0x225C. */

/* func_ceq_csr Base address of Module's Register */
#define CSR_FUNC_CEQ_CSR_BASE (0x4281000)

/* **************************************************************************** */
/*                      func_ceq_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_FUNC_CEQ_CSR_CEQ_CTL_0_0_REG                                                                          \
    (CSR_FUNC_CEQ_CSR_BASE + 0x0) /* Each PF use offset = 0x280 to access this csr after correct configuration of \
                                     CEQ_INDIR_IDX.VF offset = 0x2280. */
#define CSR_FUNC_CEQ_CSR_CEQ_CTL_0_1_REG                                                                           \
    (CSR_FUNC_CEQ_CSR_BASE + 0x80) /* Each PF use offset = 0x280 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x2280. */
#define CSR_FUNC_CEQ_CSR_CEQ_CTL_1_0_REG                                                                          \
    (CSR_FUNC_CEQ_CSR_BASE + 0x4) /* Each PF use offset = 0x284 to access this csr after correct configuration of \
                                     CEQ_INDIR_IDX.VF offset = 0x2284. */
#define CSR_FUNC_CEQ_CSR_CEQ_CTL_1_1_REG                                                                           \
    (CSR_FUNC_CEQ_CSR_BASE + 0x84) /* Each PF use offset = 0x284 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x2284. */
#define CSR_FUNC_CEQ_CSR_CEQ_CI_0_REG                                                                             \
    (CSR_FUNC_CEQ_CSR_BASE + 0x8) /* Each PF use offset = 0x288 to access this csr after correct configuration of \
                                     CEQ_INDIR_IDX.VF offset = 0x2288. */
#define CSR_FUNC_CEQ_CSR_CEQ_CI_1_REG                                                                              \
    (CSR_FUNC_CEQ_CSR_BASE + 0x88) /* Each PF use offset = 0x288 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x2288. */
#define CSR_FUNC_CEQ_CSR_CEQ_PI_0_REG                                                                             \
    (CSR_FUNC_CEQ_CSR_BASE + 0xC) /* Each PF use offset = 0x28C to access this csr after correct configuration of \
                                     CEQ_INDIR_IDX.VF offset = 0x228C. */
#define CSR_FUNC_CEQ_CSR_CEQ_PI_1_REG                                                                              \
    (CSR_FUNC_CEQ_CSR_BASE + 0x8C) /* Each PF use offset = 0x28C to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x228C. */
#define CSR_FUNC_CEQ_CSR_CEQ_INDIR_IDX_0_REG \
    (CSR_FUNC_CEQ_CSR_BASE +                 \
        0x10) /* Each PF use offset = 0x290 to access this csr. VF offset = 0x2290.MPU can't access this CSR. */
#define CSR_FUNC_CEQ_CSR_CEQ_INDIR_IDX_1_REG \
    (CSR_FUNC_CEQ_CSR_BASE +                 \
        0x90) /* Each PF use offset = 0x290 to access this csr. VF offset = 0x2290.MPU can't access this CSR. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x40) /* Each PF use offset = 0x2C0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22C0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xC0) /* Each PF use offset = 0x2C0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22C0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x44) /* Each PF use offset = 0x2C4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22C4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xC4) /* Each PF use offset = 0x2C4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22C4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x48) /* Each PF use offset = 0x2C8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22C8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xC8) /* Each PF use offset = 0x2C8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22C8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x4C) /* Each PF use offset = 0x2CC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22CC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xCC) /* Each PF use offset = 0x2CC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22CC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x50) /* Each PF use offset = 0x2D0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22D0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xD0) /* Each PF use offset = 0x2D0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22D0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x54) /* Each PF use offset = 0x2D4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22D4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xD4) /* Each PF use offset = 0x2D4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22D4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x58) /* Each PF use offset = 0x2D8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22D8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xD8) /* Each PF use offset = 0x2D8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22D8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x5C) /* Each PF use offset = 0x2DC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22DC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xDC) /* Each PF use offset = 0x2DC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22DC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x60) /* Each PF use offset = 0x2E0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22E0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xE0) /* Each PF use offset = 0x2E0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22E0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x64) /* Each PF use offset = 0x2E4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22E4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xE4) /* Each PF use offset = 0x2E4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22E4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x68) /* Each PF use offset = 0x2E8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22E8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xE8) /* Each PF use offset = 0x2E8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22E8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x6C) /* Each PF use offset = 0x2EC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22EC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xEC) /* Each PF use offset = 0x2EC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22EC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x70) /* Each PF use offset = 0x2F0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22F0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xF0) /* Each PF use offset = 0x2F0 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22F0. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x74) /* Each PF use offset = 0x2F4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22F4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xF4) /* Each PF use offset = 0x2F4 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22F4. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_H_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x78) /* Each PF use offset = 0x2F8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22F8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_H_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xF8) /* Each PF use offset = 0x2F8 to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22F8. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_L_0_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0x7C) /* Each PF use offset = 0x2FC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22FC. */
#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_L_1_REG                                                                 \
    (CSR_FUNC_CEQ_CSR_BASE + 0xFC) /* Each PF use offset = 0x2FC to access this csr after correct configuration of \
                                      CEQ_INDIR_IDX.VF offset = 0x22FC. */

/* func_int_csr Base address of Module's Register */
#define CSR_FUNC_INT_CSR_BASE (0x4301000)

/* **************************************************************************** */
/*                      func_int_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_0_0_REG                                                                  \
    (CSR_FUNC_INT_CSR_BASE + 0x0) /* Each PF use offset = 0x300 to access this csr after correct configuration of \
                                     MSI_CONTROL_INDIR_IDX. VF offset = 0x2300. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_0_1_REG                                                                   \
    (CSR_FUNC_INT_CSR_BASE + 0x20) /* Each PF use offset = 0x300 to access this csr after correct configuration of \
                                      MSI_CONTROL_INDIR_IDX. VF offset = 0x2300. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_1_0_REG                                                                  \
    (CSR_FUNC_INT_CSR_BASE + 0x4) /* Each PF use offset = 0x304 to access this csr after correct configuration of \
                                     MSI_CONTROL_INDIR_IDX. VF offset = 0x2304. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_1_1_REG                                                                   \
    (CSR_FUNC_INT_CSR_BASE + 0x24) /* Each PF use offset = 0x304 to access this csr after correct configuration of \
                                      MSI_CONTROL_INDIR_IDX. VF offset = 0x2304. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_2_0_REG                                                                  \
    (CSR_FUNC_INT_CSR_BASE + 0x8) /* Each PF use offset = 0x308 to access this csr after correct configuration of \
                                     MSI_CONTROL_INDIR_IDX. VF offset = 0x2308. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_2_1_REG                                                                   \
    (CSR_FUNC_INT_CSR_BASE + 0x28) /* Each PF use offset = 0x308 to access this csr after correct configuration of \
                                      MSI_CONTROL_INDIR_IDX. VF offset = 0x2308. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_3_0_REG                                                                  \
    (CSR_FUNC_INT_CSR_BASE + 0xC) /* Each PF use offset = 0x30C to access this csr after correct configuration of \
                                     MSI_CONTROL_INDIR_IDX. VF offset = 0x230C. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_3_1_REG                                                                   \
    (CSR_FUNC_INT_CSR_BASE + 0x2C) /* Each PF use offset = 0x30C to access this csr after correct configuration of \
                                      MSI_CONTROL_INDIR_IDX. VF offset = 0x230C. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_INDIR_IDX_REG \
    (CSR_FUNC_INT_CSR_BASE +                       \
        0x10) /* Each PF use offset = 0x310 to access this csr. VF offset = 0x2310.MPU can't access this CSR. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_4_0_REG (CSR_FUNC_INT_CSR_BASE + 0x14) /* It is only access by MPU. */
#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_4_1_REG (CSR_FUNC_INT_CSR_BASE + 0x34) /* It is only access by MPU. */
#define CSR_FUNC_INT_CSR_FUNCTION_DMA_ATTR_ENTR_0_REG                                                                 \
    (CSR_FUNC_INT_CSR_BASE + 0x80000) /* Each PF use offset = 0x380 to access this csr after correct configuration of \
                                         DMA_ATTR_INDIR_IDX.VF offset = 0x2380. */
#define CSR_FUNC_INT_CSR_FUNCTION_DMA_ATTR_ENTR_1_REG                                                                 \
    (CSR_FUNC_INT_CSR_BASE + 0x80004) /* Each PF use offset = 0x380 to access this csr after correct configuration of \
                                         DMA_ATTR_INDIR_IDX.VF offset = 0x2380. */
#define CSR_FUNC_INT_CSR_DMA_ATTR_INDIR_IDX_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0x10) /* Each PF use offset = 0x390 to access this csr. VF offset = 0x2390.MPU can't access this CSR. */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0000) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0080) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0100) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0180) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0200) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0280) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0300) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0380) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0400) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0480) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0500) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0580) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0600) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0680) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0700) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0780) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0800) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0880) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0900) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0980) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0004) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0084) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0104) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0184) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0204) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0284) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0304) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0384) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0404) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0484) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0504) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0584) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0604) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0684) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0704) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0784) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0804) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0884) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0904) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0984) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0008) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0088) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0108) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0188) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0208) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0288) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0308) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0388) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0408) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA0488) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0508) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0588) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0608) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0688) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0708) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0788) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0808) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0888) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0908) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0988) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA000C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA008C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA010C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA018C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA020C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA028C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA030C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA038C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA040C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                 \
        0xA048C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA050C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA058C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA060C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA068C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA070C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA078C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA080C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA088C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA090C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA098C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0A8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0B8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0C8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0D8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0E8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                  \
        0xA0F8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0010) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0090) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0110) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0190) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0210) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0290) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0310) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0390) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0410) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0490) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0510) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0590) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0610) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0690) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0710) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0790) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0810) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0890) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0910) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0990) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0014) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0094) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0114) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0194) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0214) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0294) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0314) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0394) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0414) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0494) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0514) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0594) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0614) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0694) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0714) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0794) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0814) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0894) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0914) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0994) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0018) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0098) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0118) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0198) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0218) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0298) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0318) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0398) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0418) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA0498) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0518) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0598) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0618) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0698) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0718) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0798) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0818) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0898) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0918) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0998) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_0_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA001C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_1_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA009C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_2_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA011C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_3_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA019C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_4_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA021C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_5_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA029C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_6_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA031C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_7_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA039C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_8_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA041C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_9_REG \
    (CSR_FUNC_INT_CSR_BASE +                   \
        0xA049C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_10_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA051C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_11_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA059C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_12_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA061C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_13_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA069C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_14_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA071C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_15_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA079C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_16_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA081C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_17_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA089C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_18_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA091C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_19_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA099C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_20_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_21_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0A9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_22_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_23_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0B9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_24_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_25_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0C9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_26_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_27_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0D9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_28_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_29_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0E9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_30_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */
#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_31_REG \
    (CSR_FUNC_INT_CSR_BASE +                    \
        0xA0F9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */

/* host_csr Base address of Module's Register */
#define CSR_HOST_CSR_BASE (0x43AC000)

/* **************************************************************************** */
/*                      host_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HOST_CSR_PPF_ELECTION_0_REG \
    (CSR_HOST_CSR_BASE +                \
        0x0) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */
#define CSR_HOST_CSR_PPF_ELECTION_1_REG \
    (CSR_HOST_CSR_BASE +                \
        0x4) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */
#define CSR_HOST_CSR_PPF_ELECTION_2_REG \
    (CSR_HOST_CSR_BASE +                \
        0x8) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */
#define CSR_HOST_CSR_PPF_ELECTION_3_REG \
    (CSR_HOST_CSR_BASE +                \
        0xC) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */
#define CSR_HOST_CSR_PPF_ELECTION_4_REG \
    (CSR_HOST_CSR_BASE +                \
        0x10) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */
#define CSR_HOST_CSR_MPF_ELECTION_REG \
    (CSR_HOST_CSR_BASE +              \
        0x20) /* MPF election.(each PF will use offset=0x020 to access this CSR)此地址不受直接访问权限控制。 */
#define CSR_HOST_CSR_UCPU_CLP_SIZE_0_REG \
    (CSR_HOST_CSR_BASE + 0x40) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_SIZE_1_REG \
    (CSR_HOST_CSR_BASE + 0x60) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_SIZE_2_REG \
    (CSR_HOST_CSR_BASE + 0x80) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_SIZE_3_REG \
    (CSR_HOST_CSR_BASE + 0xA0) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQBASE_0_REG \
    (CSR_HOST_CSR_BASE + 0x44) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQBASE_1_REG \
    (CSR_HOST_CSR_BASE + 0x64) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQBASE_2_REG \
    (CSR_HOST_CSR_BASE + 0x84) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQBASE_3_REG \
    (CSR_HOST_CSR_BASE + 0xA4) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_0_REG \
    (CSR_HOST_CSR_BASE + 0x48) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_1_REG \
    (CSR_HOST_CSR_BASE + 0x68) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_2_REG \
    (CSR_HOST_CSR_BASE + 0x88) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_3_REG \
    (CSR_HOST_CSR_BASE + 0xA8) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQ_0_REG \
    (CSR_HOST_CSR_BASE + 0x4C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQ_1_REG \
    (CSR_HOST_CSR_BASE + 0x6C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQ_2_REG \
    (CSR_HOST_CSR_BASE + 0x8C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_REQ_3_REG \
    (CSR_HOST_CSR_BASE + 0xAC) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSP_0_REG \
    (CSR_HOST_CSR_BASE + 0x50) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSP_1_REG \
    (CSR_HOST_CSR_BASE + 0x70) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSP_2_REG \
    (CSR_HOST_CSR_BASE + 0x90) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */
#define CSR_HOST_CSR_UCPU_CLP_RSP_3_REG \
    (CSR_HOST_CSR_BASE + 0xB0) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */
#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_0_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xC0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */
#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_1_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xC8) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */
#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_2_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xD0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */
#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_3_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xD8) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */
#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_4_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xE0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */
#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_0_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xC4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */
#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_1_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xCC) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */
#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_2_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xD4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */
#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_3_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xDC) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */
#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_4_REG \
    (CSR_HOST_CSR_BASE +                       \
        0xE4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x100) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x104) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x108) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x10C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x110) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x114) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x118) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x11C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x120) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x124) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x128) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x12C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x130) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x134) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x138) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x13C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x140) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x144) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x148) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x14C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x150) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x154) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x158) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x15C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x160) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x164) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x168) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x16C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x170) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x174) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x178) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x17C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x180) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x184) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x188) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x18C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x190) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x194) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x198) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x19C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x1A0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x1A4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1A8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1AC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1B0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1B4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1B8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1BC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1C0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1C4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1C8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1CC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1D0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1D4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1D8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1DC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1E0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1E4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1E8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1EC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1F0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1F4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1F8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x1FC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x200) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x204) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x208) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x20C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x210) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x214) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x218) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x21C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x220) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x224) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x228) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x22C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x230) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x234) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x238) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x23C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x240) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x244) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x248) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x24C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x250) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x254) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x258) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x25C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x260) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x264) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x268) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x26C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x270) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x274) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x278) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x27C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x280) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x284) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x288) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x28C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x290) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x294) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x298) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x29C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x2A0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x2A4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2A8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2AC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2B0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2B4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2B8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2BC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2C0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2C4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2C8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2CC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2D0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2D4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2D8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2DC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2E0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2E4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2E8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2EC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2F0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2F4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2F8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x2FC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x300) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x304) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x308) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x30C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x310) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x314) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x318) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x31C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x320) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x324) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x328) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x32C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x330) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x334) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x338) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x33C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x340) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x344) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x348) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x34C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x350) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x354) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x358) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x35C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x360) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x364) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x368) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x36C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x370) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x374) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x378) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x37C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x380) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x384) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x388) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x38C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x390) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x394) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x398) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x39C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x3A0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x3A4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3A8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3AC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3B0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3B4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3B8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3BC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3C0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3C4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3C8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3CC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3D0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3D4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3D8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3DC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3E0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3E4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3E8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3EC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3F0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3F4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3F8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x3FC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x400) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x404) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x408) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x40C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x410) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x414) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x418) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x41C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x420) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x424) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x428) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x42C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x430) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x434) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x438) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x43C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x440) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x444) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x448) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x44C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x450) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x454) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x458) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x45C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x460) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x464) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x468) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x46C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x470) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x474) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x478) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x47C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x480) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x484) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x488) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x48C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x490) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x494) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x498) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x49C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x4A0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x4A4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4A8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4AC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4B0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4B4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4B8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4BC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4C0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4C4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4C8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4CC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4D0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4D4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4D8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4DC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4E0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4E4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4E8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4EC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4F0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4F4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4F8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x4FC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x500) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x504) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x508) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x50C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x510) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x514) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x518) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x51C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x520) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x524) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x528) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x52C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x530) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x534) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x538) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x53C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x540) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x544) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x548) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x54C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x550) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x554) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x558) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x55C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x560) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x564) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x568) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x56C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x570) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x574) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x578) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x57C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x100~0x17C to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_0_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x580) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_1_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x584) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_2_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x588) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_3_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x58C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_4_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x590) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_5_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x594) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_6_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x598) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_7_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x59C) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_8_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x5A0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_9_REG                                                           \
    (CSR_HOST_CSR_BASE + 0x5A4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_10_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5A8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_11_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5AC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_12_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5B0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_13_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5B4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_14_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5B8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_15_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5BC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_16_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5C0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_17_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5C4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_18_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5C8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_19_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5CC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_20_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5D0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_21_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5D4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_22_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5D8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_23_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5DC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_24_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5E0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_25_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5E4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_26_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5E8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_27_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5EC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_28_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5F0) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_29_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5F4) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_30_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5F8) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */
#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_31_REG                                                          \
    (CSR_HOST_CSR_BASE + 0x5FC) /* data registers for communication between host and MPU.(each PF will use \
                                   offset=0x180~0x1FC to access corresponding host CSRs) */

/* glb_csr Base address of Module's Register */
#define CSR_GLB_CSR_BASE (0x43AD000)

/* **************************************************************************** */
/*                      glb_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_GLB_CSR_GLB_CPI_VERSION_CSR_REG (CSR_GLB_CSR_BASE + 0x0)
#define CSR_GLB_CSR_GLB_X86_REQ_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x4)
#define CSR_GLB_CSR_GLB_X86_CPL_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x8)
#define CSR_GLB_CSR_GLB_SPU_X86_ACC_WEIGHT_REG (CSR_GLB_CSR_BASE + 0xC)
#define CSR_GLB_CSR_GLB_PORT_MODE_REG (CSR_GLB_CSR_BASE + 0x10)
#define CSR_GLB_CSR_GLB_SPU_REQ_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x14)
#define CSR_GLB_CSR_GLB_SPU_CPL_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x18)
#define CSR_GLB_CSR_GLB_RES_PER_FUNC_REG (CSR_GLB_CSR_BASE + 0x50) /* The global resources for each function */
#define CSR_GLB_CSR_API_GAP_CTL_REG (CSR_GLB_CSR_BASE + 0x54)      /* API sending gap configuration */
#define CSR_GLB_CSR_DIR_WQE_GAP_CTL_REG (CSR_GLB_CSR_BASE + 0x58)  /* Direct WQE sending gap configuration */
#define CSR_GLB_CSR_DIR_WQE_TIMEOUT_REG (CSR_GLB_CSR_BASE + 0x5C)  /* Direct WQE timeout configuration */
#define CSR_GLB_CSR_GLB_SW_SRCH_TCAM_CTL_REG (CSR_GLB_CSR_BASE + 0x80)
#define CSR_GLB_CSR_GLB_SW_SRCH_TCAM_RSLT_REG (CSR_GLB_CSR_BASE + 0x84)
#define CSR_GLB_CSR_GLB_APB_TIMER_CFG_REG (CSR_GLB_CSR_BASE + 0x88) /* The threshold for wait timer in the I_CTL */
#define CSR_GLB_CSR_GLB_SRV_TYPE_FOR_DDB_REG \
    (CSR_GLB_CSR_BASE + 0x8C) /* The Srv_Type in the doorbell API generated by direct WQE */
#define CSR_GLB_CSR_GLB_NL2N_INLINE_OTD_REG (CSR_GLB_CSR_BASE + 0x90) /* Outstanding of NL2N sub-command */
#define CSR_GLB_CSR_GLB_NL2N_INLINE_NUM_TH_REG \
    (CSR_GLB_CSR_BASE + 0x94)                                        /* Upper threshold of local NL2N sub-command. */
#define CSR_GLB_CSR_GLB_TILEP_POLL_GAP_REG (CSR_GLB_CSR_BASE + 0x98) /* Poll gap of tile proxy */
#define CSR_GLB_CSR_GLB_MB_TX_LEGAL_CHK_REG \
    (CSR_GLB_CSR_BASE + 0xA0)                                  /* check the mailbox sendor and receiver whether legal */
#define CSR_GLB_CSR_GLB_CPL_CTRL_REG (CSR_GLB_CSR_BASE + 0xA8) /* CPL Control */
#define CSR_GLB_CSR_UCPU_MB_TX_CTL_REG (CSR_GLB_CSR_BASE + 0xB0)      /* the UCPU MB send control */
#define CSR_GLB_CSR_UCPU_ALLOW_VF_CFG_REG (CSR_GLB_CSR_BASE + 0xBC)   /* the UCPU alow VF have configure right */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_0_REG (CSR_GLB_CSR_BASE + 0xC0)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_1_REG (CSR_GLB_CSR_BASE + 0xC4)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_2_REG (CSR_GLB_CSR_BASE + 0xC8)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_3_REG (CSR_GLB_CSR_BASE + 0xCC)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_4_REG (CSR_GLB_CSR_BASE + 0xD0)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_5_REG (CSR_GLB_CSR_BASE + 0xD4)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_6_REG (CSR_GLB_CSR_BASE + 0xD8)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_7_REG (CSR_GLB_CSR_BASE + 0xDC)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_8_REG (CSR_GLB_CSR_BASE + 0xE0)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_9_REG (CSR_GLB_CSR_BASE + 0xE4)   /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_10_REG (CSR_GLB_CSR_BASE + 0xE8)  /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_11_REG (CSR_GLB_CSR_BASE + 0xEC)  /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_12_REG (CSR_GLB_CSR_BASE + 0xF0)  /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_13_REG (CSR_GLB_CSR_BASE + 0xF4)  /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_14_REG (CSR_GLB_CSR_BASE + 0xF8)  /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_UCPU_MB_TX_DATA_15_REG (CSR_GLB_CSR_BASE + 0xFC)  /* the UCPU MB data to be sent */
#define CSR_GLB_CSR_PF_EPROM_OFFSET_BASE_REG (CSR_GLB_CSR_BASE + 0x100)  /* The Expansion ROM offset configuration */
#define CSR_GLB_CSR_CPI_TBL_INDIR_CTRL0_REG \
    (CSR_GLB_CSR_BASE + 0x200) /* CPI internal table indirect access ctrl registers */
#define CSR_GLB_CSR_CPI_TBL_INDIR_CTRL1_REG \
    (CSR_GLB_CSR_BASE + 0x204) /* CPI internal table indirect access ctrl registers */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_0_REG (CSR_GLB_CSR_BASE + 0x210) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_1_REG (CSR_GLB_CSR_BASE + 0x214) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_2_REG (CSR_GLB_CSR_BASE + 0x218) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_3_REG (CSR_GLB_CSR_BASE + 0x21C) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_4_REG (CSR_GLB_CSR_BASE + 0x220) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_5_REG (CSR_GLB_CSR_BASE + 0x224) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_6_REG (CSR_GLB_CSR_BASE + 0x228) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_7_REG (CSR_GLB_CSR_BASE + 0x22C) /* CPI internal table indirect access data */
#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_CTRL_REG (CSR_GLB_CSR_BASE + 0x230) /* pcie indir to ring path control */
#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_DAT0_REG (CSR_GLB_CSR_BASE + 0x234) /* pcie indir to ring path data0 */
#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_DAT1_REG (CSR_GLB_CSR_BASE + 0x238) /* pcie indir to ring path data0 */
#define CSR_GLB_CSR_CPI_RAM_INIT_REQ_REG (CSR_GLB_CSR_BASE + 0x240)         /* CPI internal RAM initial request */
#define CSR_GLB_CSR_CPI_RAM_INIT_STS0_REG (CSR_GLB_CSR_BASE + 0x250)        /* CPI internal RAM initial status 0 */
#define CSR_GLB_CSR_CPI_RAM_INIT_STS1_REG (CSR_GLB_CSR_BASE + 0x254)        /* CPI internal RAM initial status 1 */
#define CSR_GLB_CSR_CPI_MB_TX_GAP_REG (CSR_GLB_CSR_BASE + 0x260)            /* CPI control the mailobx sending gap */
#define CSR_GLB_CSR_GLB_CPI_RAM_ECC_BYPASS_REG (CSR_GLB_CSR_BASE + 0x280)   /* CPI internal RAM test mode */
#define CSR_GLB_CSR_GLB_MB_SHP_HOST0_REG (CSR_GLB_CSR_BASE + 0x290)         /* mailbox shaper control csr for host0 */
#define CSR_GLB_CSR_GLB_MB_SHP_HOST1_REG (CSR_GLB_CSR_BASE + 0x294)         /* mailbox shaper control csr for host1 */
#define CSR_GLB_CSR_GLB_MB_SHP_HOST2_REG (CSR_GLB_CSR_BASE + 0x298)         /* mailbox shaper control csr for host2 */
#define CSR_GLB_CSR_GLB_MB_SHP_HOST3_REG (CSR_GLB_CSR_BASE + 0x29C)         /* mailbox shaper control csr for host3 */
#define CSR_GLB_CSR_GLB_MB_SHP_HOST4_REG (CSR_GLB_CSR_BASE + 0x2A0)         /* mailbox shaper control csr for host4 */
#define CSR_GLB_CSR_GLB_MB_SHP_UNIT_REG (CSR_GLB_CSR_BASE + 0x2A4)          /* mailbox shaper time unit */
#define CSR_GLB_CSR_GLB_MB_RIGHT_CFG_REG (CSR_GLB_CSR_BASE + 0x2A8)
#define CSR_GLB_CSR_GLB_CSR_ACC_TIMEOUT_REG (CSR_GLB_CSR_BASE + 0x2B0)
#define CSR_GLB_CSR_GLB_CPI_RS_ND_PE_CRDIT_REG (CSR_GLB_CSR_BASE + 0x2B8)
#define CSR_GLB_CSR_GLB_NP_CTX_CFG_REG (CSR_GLB_CSR_BASE + 0x2F0)
#define CSR_GLB_CSR_GLB_IPUSH_FIFO_BP_REG (CSR_GLB_CSR_BASE + 0x318)
#define CSR_GLB_CSR_GLB_IPUSH_FIFO_STS_REG (CSR_GLB_CSR_BASE + 0x31C)
#define CSR_GLB_CSR_GLB_CPATH_INT_BITMAP_REG (CSR_GLB_CSR_BASE + 0x340)  /* non-cpi INT的中断屏蔽寄存器 */
#define CSR_GLB_CSR_GLB_DWQE_BUF_VLD_NUM_REG (CSR_GLB_CSR_BASE + 0x344)  /* Direct WQE Buffer的可用参数 */
#define CSR_GLB_CSR_DIR_WQE_BYTE_ORDER_EN_REG (CSR_GLB_CSR_BASE + 0x354) /* Direct WQE字节序转换使能 */
#define CSR_GLB_CSR_FAKE_VFID_CAL_CFG_REG (CSR_GLB_CSR_BASE + 0x360)     /* fake VFID此寄存器配置要保证全局一致。 */
#define CSR_GLB_CSR_FAKE_VFID_ENABLE_REG (CSR_GLB_CSR_BASE + 0x364)      /* fake VFID此寄存器配置要保证全局一致。 */
#define CSR_GLB_CSR_DBL_FAKE_VFID_CBIT_EN_REG (CSR_GLB_CSR_BASE + 0x368)
#define CSR_GLB_CSR_DBL_SRV_TYPE_ILLEGAL_REG (CSR_GLB_CSR_BASE + 0x36C)
#define CSR_GLB_CSR_GLB_DWQE_LB_HASH_ACC_REG (CSR_GLB_CSR_BASE + 0x370)  /* load balance此寄存器配置要保证全局一致。 */
#define CSR_GLB_CSR_GLB_DWQE_LB_MOD_REG (CSR_GLB_CSR_BASE + 0x374)       /* load balance此寄存器配置要保证全局一致。 */
#define CSR_GLB_CSR_GLB_DWQE_SMF_PG_REG (CSR_GLB_CSR_BASE + 0x378)       /* load balance此寄存器配置要保证全局一致。 */
#define CSR_GLB_CSR_VIRTIO_BYTE_ORDER_DIS_REG (CSR_GLB_CSR_BASE + 0x380) /* VIRTIO_ITF字节序转换disable */
#define CSR_GLB_CSR_NVME_RSV_ADDR_RANGE_REG (CSR_GLB_CSR_BASE + 0x384)
#define CSR_GLB_CSR_VIRTIO_LB_MOD_REG (CSR_GLB_CSR_BASE + 0x388)
#define CSR_GLB_CSR_VIRTIO_OTD_MAX_TH_REG (CSR_GLB_CSR_BASE + 0x38C)
#define CSR_GLB_CSR_GLB_FLXQ_MAP_EN_REG (CSR_GLB_CSR_BASE + 0x390)
#define CSR_GLB_CSR_GLB_AEQ_IDX_FOR_VF_REG (CSR_GLB_CSR_BASE + 0x3A0) /* 第一个VF所对应物理资源AEQ的起始编号。 */
#define CSR_GLB_CSR_PTP_TS_UPDT_CFG_REG (CSR_GLB_CSR_BASE + 0x3AC)    /* Timestamp timer update */
#define CSR_GLB_CSR_PTP_TS_INC_CFG_REG (CSR_GLB_CSR_BASE + 0x3B0)     /* Timestamp timer configuration */
#define CSR_GLB_CSR_PTP_TS_CALIBRATION_REG (CSR_GLB_CSR_BASE + 0x3B4) /* Timestamp timer calibration */
#define CSR_GLB_CSR_PTP_TS_WR_DATA0_REG (CSR_GLB_CSR_BASE + 0x3B8)    /* Timestamp timer write data 0 */
#define CSR_GLB_CSR_PTP_TS_WR_DATA1_REG (CSR_GLB_CSR_BASE + 0x3BC)    /* Timestamp timer write data 1 */
#define CSR_GLB_CSR_PTP_TS_WR_DATA2_REG (CSR_GLB_CSR_BASE + 0x3C0)    /* Timestamp timer write data 2 */
#define CSR_GLB_CSR_PTP_TS_RD_DATA0_REG (CSR_GLB_CSR_BASE + 0x3C4)    /* Timestamp timer read data 0 */
#define CSR_GLB_CSR_PTP_TS_RD_DATA1_REG (CSR_GLB_CSR_BASE + 0x3C8)    /* Timestamp timer read data 1 */
#define CSR_GLB_CSR_PTP_TS_RD_DATA2_REG (CSR_GLB_CSR_BASE + 0x3CC)    /* Timestamp timer read data 2 */
#define CSR_GLB_CSR_PTP_TS_UP_EN_REG \
    (CSR_GLB_CSR_BASE +              \
        0x3D0) /* Timestamp timer update enableAttention, bit[3:0] should be configured in onehot mode. */
#define CSR_GLB_CSR_PTP_DSTR_CFG_REG (CSR_GLB_CSR_BASE + 0x3D4)           /* Timestamp distribute configuration */
#define CSR_GLB_CSR_NON_PTP_TS_INC_CFG_REG (CSR_GLB_CSR_BASE + 0x3D8)     /* non-MAC Timestamp timer configuration */
#define CSR_GLB_CSR_NON_PTP_TS_CALIBRATION_REG (CSR_GLB_CSR_BASE + 0x3DC) /* non-MAC Timestamp timer calibration */
#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA0_REG (CSR_GLB_CSR_BASE + 0x3E0)    /* non-MAC Timestamp timer write data 0 */
#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA1_REG (CSR_GLB_CSR_BASE + 0x3E4)    /* non-MAC Timestamp timer write data 1 */
#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA2_REG (CSR_GLB_CSR_BASE + 0x3E8)    /* non-MAC Timestamp timer write data 2 */
#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA0_REG (CSR_GLB_CSR_BASE + 0x3EC)    /* non-MAC Timestamp timer read data 0 */
#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA1_REG (CSR_GLB_CSR_BASE + 0x3F0)    /* non-MAC Timestamp timer read data 1 */
#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA2_REG (CSR_GLB_CSR_BASE + 0x3F4)    /* non-MAC Timestamp timer read data 2 */
#define CSR_GLB_CSR_NON_PTP_TS_UP_EN_REG \
    (CSR_GLB_CSR_BASE +                  \
        0x3F8) /* non-MAC Timestamp timer update enable.Attention, bit[2:0] should be configured in onehot mode. */
#define CSR_GLB_CSR_NON_PTP_DSTR_CFG_REG (CSR_GLB_CSR_BASE + 0x3FC) /* non-MAC Timestamp distribute configuration */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_0_REG (CSR_GLB_CSR_BASE + 0x400)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_1_REG (CSR_GLB_CSR_BASE + 0x404)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_2_REG (CSR_GLB_CSR_BASE + 0x408)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_3_REG (CSR_GLB_CSR_BASE + 0x40C)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_4_REG (CSR_GLB_CSR_BASE + 0x410)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_5_REG (CSR_GLB_CSR_BASE + 0x414)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_6_REG (CSR_GLB_CSR_BASE + 0x418)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_7_REG (CSR_GLB_CSR_BASE + 0x41C)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_8_REG (CSR_GLB_CSR_BASE + 0x420)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_9_REG (CSR_GLB_CSR_BASE + 0x424)  /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_10_REG (CSR_GLB_CSR_BASE + 0x428) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_11_REG (CSR_GLB_CSR_BASE + 0x42C) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_12_REG (CSR_GLB_CSR_BASE + 0x430) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_13_REG (CSR_GLB_CSR_BASE + 0x434) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_14_REG (CSR_GLB_CSR_BASE + 0x438) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_15_REG (CSR_GLB_CSR_BASE + 0x43C) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_16_REG (CSR_GLB_CSR_BASE + 0x440) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_17_REG (CSR_GLB_CSR_BASE + 0x444) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_18_REG (CSR_GLB_CSR_BASE + 0x448) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_19_REG (CSR_GLB_CSR_BASE + 0x44C) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_20_REG (CSR_GLB_CSR_BASE + 0x450) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_21_REG (CSR_GLB_CSR_BASE + 0x454) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_22_REG (CSR_GLB_CSR_BASE + 0x458) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_23_REG (CSR_GLB_CSR_BASE + 0x45C) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_24_REG (CSR_GLB_CSR_BASE + 0x460) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_25_REG (CSR_GLB_CSR_BASE + 0x464) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_26_REG (CSR_GLB_CSR_BASE + 0x468) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_27_REG (CSR_GLB_CSR_BASE + 0x46C) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_28_REG (CSR_GLB_CSR_BASE + 0x470) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_29_REG (CSR_GLB_CSR_BASE + 0x474) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_30_REG (CSR_GLB_CSR_BASE + 0x478) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_31_REG (CSR_GLB_CSR_BASE + 0x47C) /* vf offset for the PF */
#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_32_REG (CSR_GLB_CSR_BASE + 0x480) /* vf offset for the PF */

/* api_chn_csr Base address of Module's Register */
#define CSR_API_CHN_CSR_BASE (0x43A4000)

/* **************************************************************************** */
/*                      api_chn_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_API_CHN_CSR_API_CHAIN_ADDR_H_0_REG \
    (CSR_API_CHN_CSR_BASE +                    \
        0x0) /* high 32 bits address of an API chain一个PF最多分配128份api chain资源。全局共有256份api chain资源。 */
#define CSR_API_CHN_CSR_API_CHAIN_ADDR_H_1_REG \
    (CSR_API_CHN_CSR_BASE +                    \
        0x80) /* high 32 bits address of an API chain一个PF最多分配128份api chain资源。全局共有256份api chain资源。 */
#define CSR_API_CHN_CSR_API_CHAIN_ADDR_L_0_REG (CSR_API_CHN_CSR_BASE + 0x4)  /* low 32 bits address of an API chain */
#define CSR_API_CHN_CSR_API_CHAIN_ADDR_L_1_REG (CSR_API_CHN_CSR_BASE + 0x84) /* low 32 bits address of an API chain */
#define CSR_API_CHN_CSR_API_STATUS_ADDR_H_0_REG \
    (CSR_API_CHN_CSR_BASE + 0x8) /* High 32 bits address to write back status */
#define CSR_API_CHN_CSR_API_STATUS_ADDR_H_1_REG \
    (CSR_API_CHN_CSR_BASE + 0x88) /* High 32 bits address to write back status */
#define CSR_API_CHN_CSR_API_STATUS_ADDR_L_0_REG \
    (CSR_API_CHN_CSR_BASE + 0xC) /* Low 32 bits address to write back status */
#define CSR_API_CHN_CSR_API_STATUS_ADDR_L_1_REG \
    (CSR_API_CHN_CSR_BASE + 0x8C)                                         /* Low 32 bits address to write back status */
#define CSR_API_CHN_CSR_API_CHAIN_LEN_0_REG (CSR_API_CHN_CSR_BASE + 0x10) /* The API chain length */
#define CSR_API_CHN_CSR_API_CHAIN_LEN_1_REG (CSR_API_CHN_CSR_BASE + 0x90) /* The API chain length */
#define CSR_API_CHN_CSR_API_CHAIN_CTL_0_REG (CSR_API_CHN_CSR_BASE + 0x14) /* API chain attribute */
#define CSR_API_CHN_CSR_API_CHAIN_CTL_1_REG (CSR_API_CHN_CSR_BASE + 0x94) /* API chain attribute */
#define CSR_API_CHN_CSR_API_CHAIN_DMA_ATTR_0_REG (CSR_API_CHN_CSR_BASE + 0x18) /* API TPH control filed */
#define CSR_API_CHN_CSR_API_CHAIN_DMA_ATTR_1_REG (CSR_API_CHN_CSR_BASE + 0x98) /* API TPH control filed */
#define CSR_API_CHN_CSR_API_CHAIN_PI_0_REG (CSR_API_CHN_CSR_BASE + 0x1C)       /* The PI value of an API chain */
#define CSR_API_CHN_CSR_API_CHAIN_PI_1_REG (CSR_API_CHN_CSR_BASE + 0x9C)       /* The PI value of an API chain */
#define CSR_API_CHN_CSR_API_CHAIN_REQ_0_REG (CSR_API_CHN_CSR_BASE + 0x20)      /* API chain control */
#define CSR_API_CHN_CSR_API_CHAIN_REQ_1_REG (CSR_API_CHN_CSR_BASE + 0xA0)      /* API chain control */
#define CSR_API_CHN_CSR_API_STATUS_0_0_REG (CSR_API_CHN_CSR_BASE + 0x30)       /* API Chain Status */
#define CSR_API_CHN_CSR_API_STATUS_0_1_REG (CSR_API_CHN_CSR_BASE + 0xB0)       /* API Chain Status */
#define CSR_API_CHN_CSR_API_STATUS_1_0_REG (CSR_API_CHN_CSR_BASE + 0x34)       /* API Chain Current Address H */
#define CSR_API_CHN_CSR_API_STATUS_1_1_REG (CSR_API_CHN_CSR_BASE + 0xB4)       /* API Chain Current Address H */
#define CSR_API_CHN_CSR_API_STATUS_2_0_REG (CSR_API_CHN_CSR_BASE + 0x38)       /* API Chain Current Address L */
#define CSR_API_CHN_CSR_API_STATUS_2_1_REG (CSR_API_CHN_CSR_BASE + 0xB8)       /* API Chain Current Address L */

/* dfx_glb_csr Base address of Module's Register */
#define CSR_DFX_GLB_CSR_BASE (0x43AF000)

/* **************************************************************************** */
/*                      dfx_glb_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_0_REG (CSR_DFX_GLB_CSR_BASE + 0x0)           /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_1_REG (CSR_DFX_GLB_CSR_BASE + 0x10)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_2_REG (CSR_DFX_GLB_CSR_BASE + 0x20)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_3_REG (CSR_DFX_GLB_CSR_BASE + 0x30)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_4_REG (CSR_DFX_GLB_CSR_BASE + 0x40)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_5_REG (CSR_DFX_GLB_CSR_BASE + 0x50)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_6_REG (CSR_DFX_GLB_CSR_BASE + 0x60)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_7_REG (CSR_DFX_GLB_CSR_BASE + 0x70)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_8_REG (CSR_DFX_GLB_CSR_BASE + 0x80)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_9_REG (CSR_DFX_GLB_CSR_BASE + 0x90)          /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA0)         /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB0)         /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC0)         /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD0)         /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE0)         /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF0)         /* CPI debug control */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0x4)    /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x14)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x24)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x34)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x44)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x54)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x64)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x74)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x84)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x94)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA4)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB4)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC4)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD4)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE4)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF4)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0x8)    /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x18)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x28)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x38)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x48)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x58)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x68)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x78)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x88)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x98)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA8)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB8)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC8)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD8)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE8)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF8)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0xC)   /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x1C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x2C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x3C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x4C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x5C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x6C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x7C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x8C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x9C)  /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xAC) /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xBC) /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xCC) /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xDC) /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xEC) /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xFC) /* CPI debug Rx TLP counter */
#define CSR_DFX_GLB_CSR_GLB_PORT0_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x100)
#define CSR_DFX_GLB_CSR_GLB_PORT1_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x104)
#define CSR_DFX_GLB_CSR_GLB_PORT2_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x108)
#define CSR_DFX_GLB_CSR_GLB_PORT3_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x10C)
#define CSR_DFX_GLB_CSR_GLB_PORT4_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x110)
#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_OK_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x114)
#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x118)
#define CSR_DFX_GLB_CSR_DFX_ICTL_SOP_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x11C)
#define CSR_DFX_GLB_CSR_DFX_ICTL_MPU_ACC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x120)
#define CSR_DFX_GLB_CSR_DFX_ICTL_IPUSH_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x124)
#define CSR_DFX_GLB_CSR_DFX_ICTL_VIO_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x128)
#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_IO_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x12C)
#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_TLP_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x130)
#define CSR_DFX_GLB_CSR_GLB_CPI_PORT_BP_EN_CFG_REG (CSR_DFX_GLB_CSR_BASE + 0x134)
#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK0_REG (CSR_DFX_GLB_CSR_BASE + 0x140)
#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK1_REG (CSR_DFX_GLB_CSR_BASE + 0x144)
#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK2_REG (CSR_DFX_GLB_CSR_BASE + 0x148)
#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK0_REG (CSR_DFX_GLB_CSR_BASE + 0x150)
#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK1_REG (CSR_DFX_GLB_CSR_BASE + 0x154)
#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK2_REG (CSR_DFX_GLB_CSR_BASE + 0x158)
#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS0_REG (CSR_DFX_GLB_CSR_BASE + 0x160)
#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS1_REG (CSR_DFX_GLB_CSR_BASE + 0x164)
#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS2_REG (CSR_DFX_GLB_CSR_BASE + 0x168)
#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x400)    /* CPI BP WATCH Status */
#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_WINDOW_REG (CSR_DFX_GLB_CSR_BASE + 0x404) /* CPI backpressure watch window */
#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_BITMAP_REG (CSR_DFX_GLB_CSR_BASE + 0x408) /* CPI backpressure watch bitmap */
#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_START_REG (CSR_DFX_GLB_CSR_BASE + 0x40C)  /* CPI backpressure watch start */
#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x410)    /* CPI backpressure watch counter */
#define CSR_DFX_GLB_CSR_GLB_CSR_TIMEOUT_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x414)
#define CSR_DFX_GLB_CSR_DWQE_API_NO_ENOUGH_DATA_REG (CSR_DFX_GLB_CSR_BASE + 0x418)
#define CSR_DFX_GLB_CSR_DWQE_DBL_NO_ENOUGH_DATA_REG (CSR_DFX_GLB_CSR_BASE + 0x41C)
#define CSR_DFX_GLB_CSR_NORM_DBL_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x420)
#define CSR_DFX_GLB_CSR_NORM_DBL_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x424)
#define CSR_DFX_GLB_CSR_DWQE_DBL_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x428)
#define CSR_DFX_GLB_CSR_DWQE_API_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x42C)
#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x430)
#define CSR_DFX_GLB_CSR_DWQE_BUF_CNT_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x434)
#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_ON_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x438)
#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_OFF_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x43C)
#define CSR_DFX_GLB_CSR_DWQE_REQ_BUF_BGN_REG (CSR_DFX_GLB_CSR_BASE + 0x440)
#define CSR_DFX_GLB_CSR_DWQE_DROPPING_IN_TX_REG (CSR_DFX_GLB_CSR_BASE + 0x444)
#define CSR_DFX_GLB_CSR_DWQE_DROPPING_NO_BUF_REG (CSR_DFX_GLB_CSR_BASE + 0x448)
#define CSR_DFX_GLB_CSR_DWQE_DBL_WITHOUT_API_REG (CSR_DFX_GLB_CSR_BASE + 0x44C)
#define CSR_DFX_GLB_CSR_DWQE_TX_DBL_AFTER_API_REG (CSR_DFX_GLB_CSR_BASE + 0x450)
#define CSR_DFX_GLB_CSR_DWQE_NO_DBL_AFTER_API_REG (CSR_DFX_GLB_CSR_BASE + 0x454)
#define CSR_DFX_GLB_CSR_DWQE_BUF_OVERWRITE_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x458)
#define CSR_DFX_GLB_CSR_DWQE_BUF_AGING_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x45C)
#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_PUSH_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x460)
#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_POP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x464)
#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x468)
#define CSR_DFX_GLB_CSR_DWQE_DROPPING_INVLD_REG (CSR_DFX_GLB_CSR_BASE + 0x474)
#define CSR_DFX_GLB_CSR_DWQE_SW_FORCE_DROP_REG (CSR_DFX_GLB_CSR_BASE + 0x478)
#define CSR_DFX_GLB_CSR_ICTL_DBL_REQ_SOP_NULL_REG (CSR_DFX_GLB_CSR_BASE + 0x47C)
#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_MPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x480)
#define CSR_DFX_GLB_CSR_DFX_RX_DWQE_DDB_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x4A0)
#define CSR_DFX_GLB_CSR_DFX_RX_DWQE_DDB_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x4A4)
#define CSR_DFX_GLB_CSR_DFX_RX_DBL_SRV_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x4A8)
#define CSR_DFX_GLB_CSR_DFX_RX_DBL_SRV_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x4AC)
#define CSR_DFX_GLB_CSR_GLB_DFX_CFG_SRV_TYPE_REG (CSR_DFX_GLB_CSR_BASE + 0x4B0)
#define CSR_DFX_GLB_CSR_AEQ_CI_SW_WR_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4B4)
#define CSR_DFX_GLB_CSR_AEQ_TX_INT_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4BC)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_WR_PCIE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C0)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_WR_UCPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C4)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_RD_PCIE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C8)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_RD_UCPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4CC)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_OSCH_CPL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D0)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_ICTL_CPL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D4)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_APICTL_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D8)
#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_DST_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4DC)
#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_SRC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E0)
#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_STAT_TO_SRC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E4)
#define CSR_DFX_GLB_CSR_CPI_UCPU_MB_AEQE_TO_DST_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E8)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_AEQ_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4EC)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_CEQ_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F0)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_API_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F4)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_INTCTL_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F8)
#define CSR_DFX_GLB_CSR_CPI_IPUSH_UPITF_CLP_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4FC)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR0_REG \
    (CSR_DFX_GLB_CSR_BASE + 0x500) /* CPI internal RAM ECC error injection */
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x504)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR2_REG (CSR_DFX_GLB_CSR_BASE + 0x508)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR3_REG (CSR_DFX_GLB_CSR_BASE + 0x50C)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_MERR0_REG (CSR_DFX_GLB_CSR_BASE + 0x520)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_MERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x524)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR0_REG (CSR_DFX_GLB_CSR_BASE + 0x540)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x544)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR0_REG (CSR_DFX_GLB_CSR_BASE + 0x560)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR1_REG (CSR_DFX_GLB_CSR_BASE + 0x564)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR2_REG (CSR_DFX_GLB_CSR_BASE + 0x568)
#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR3_REG (CSR_DFX_GLB_CSR_BASE + 0x56C)
#define CSR_DFX_GLB_CSR_IPUSH_RESERVED0_REG (CSR_DFX_GLB_CSR_BASE + 0x5C0)
#define CSR_DFX_GLB_CSR_IPUSH_RESERVED1_REG (CSR_DFX_GLB_CSR_BASE + 0x5C4)
#define CSR_DFX_GLB_CSR_IPUSH_RESERVED2_REG (CSR_DFX_GLB_CSR_BASE + 0x5C8)
#define CSR_DFX_GLB_CSR_IPUSH_RESERVED3_REG (CSR_DFX_GLB_CSR_BASE + 0x5CC)
#define CSR_DFX_GLB_CSR_GLB_CPI_UNCRT_ERR_CODE0_REG (CSR_DFX_GLB_CSR_BASE + 0x5D0)
#define CSR_DFX_GLB_CSR_GLB_CPI_UNCRT_ERR_CODE1_REG (CSR_DFX_GLB_CSR_BASE + 0x5D4)
#define CSR_DFX_GLB_CSR_GLB_CPI_CRT_ERR_CODE0_REG (CSR_DFX_GLB_CSR_BASE + 0x5D8)
#define CSR_DFX_GLB_CSR_GLB_CPI_CRT_ERR_CODE1_REG (CSR_DFX_GLB_CSR_BASE + 0x5DC)
#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG0_REG (CSR_DFX_GLB_CSR_BASE + 0x5E0)
#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG1_REG (CSR_DFX_GLB_CSR_BASE + 0x5E4)
#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG2_REG (CSR_DFX_GLB_CSR_BASE + 0x5E8)
#define CSR_DFX_GLB_CSR_DWQE_BUG_DBG3_REG (CSR_DFX_GLB_CSR_BASE + 0x5EC)
#define CSR_DFX_GLB_CSR_GLB_MB_GRP_TX_REQ_H_REG (CSR_DFX_GLB_CSR_BASE + 0x5F0)
#define CSR_DFX_GLB_CSR_GLB_MB_GRP_TX_REQ_L_REG (CSR_DFX_GLB_CSR_BASE + 0x5F4)
#define CSR_DFX_GLB_CSR_GLB_MB_GRP_GRANT_H_REG (CSR_DFX_GLB_CSR_BASE + 0x5F8)
#define CSR_DFX_GLB_CSR_GLB_MB_GRP_GRANT_L_REG (CSR_DFX_GLB_CSR_BASE + 0x5FC)
#define CSR_DFX_GLB_CSR_ICTL_IPUSH_SOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x608)
#define CSR_DFX_GLB_CSR_ICTL_IPUSH_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x60C)
#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_TX_REQ_H_REG (CSR_DFX_GLB_CSR_BASE + 0x610)
#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_TX_REQ_L_REG (CSR_DFX_GLB_CSR_BASE + 0x614)
#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_GRANT_H_REG (CSR_DFX_GLB_CSR_BASE + 0x618)
#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_GRANT_L_REG (CSR_DFX_GLB_CSR_BASE + 0x61C)
#define CSR_DFX_GLB_CSR_GLB_MB_TX_START_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x620)
#define CSR_DFX_GLB_CSR_GLB_MB_TX_ILLEGAL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x624)
#define CSR_DFX_GLB_CSR_GLB_MB_TX_ILLEGAL_CODE_REG (CSR_DFX_GLB_CSR_BASE + 0x628)
#define CSR_DFX_GLB_CSR_GLB_MB_FSM_STATE_REG (CSR_DFX_GLB_CSR_BASE + 0x62C)
#define CSR_DFX_GLB_CSR_ICTL_INBD_FIFO_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x638)
#define CSR_DFX_GLB_CSR_ICTL_DBL_SOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x640)
#define CSR_DFX_GLB_CSR_ICTL_DBL_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x644)
#define CSR_DFX_GLB_CSR_DWQE_DROP_NO_WR_BUF_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x648)
#define CSR_DFX_GLB_CSR_DWQE_WR_BUF_COMPLETE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x64C)
#define CSR_DFX_GLB_CSR_NORM_DBL_RX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x690)
#define CSR_DFX_GLB_CSR_NORM_DBL_FORCE_DROP_REG (CSR_DFX_GLB_CSR_BASE + 0x694)
#define CSR_DFX_GLB_CSR_DWQE_RX_BUF_BGN_REG (CSR_DFX_GLB_CSR_BASE + 0x698)
#define CSR_DFX_GLB_CSR_DWQE_ILLEGAL_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x69C)
#define CSR_DFX_GLB_CSR_DWQE_DBL_FORCE_DROP_NO_API_REG (CSR_DFX_GLB_CSR_BASE + 0x6A0)
#define CSR_DFX_GLB_CSR_DWQE_DBL_FORCE_DROP_AFT_API_REG (CSR_DFX_GLB_CSR_BASE + 0x6A4)
#define CSR_DFX_GLB_CSR_AEQ_FSM_DBG_STATE_REG (CSR_DFX_GLB_CSR_BASE + 0x6A8)
#define CSR_DFX_GLB_CSR_GLB_UCPU_MSI_FUNC_IDX_REG \
    (CSR_DFX_GLB_CSR_BASE + 0x6B0) /* the function index when ucpu access CSRs in the INT_CTL */
#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_CTL_REG \
    (CSR_DFX_GLB_CSR_BASE + 0x6B4) /* the control register to measure the inbound itf */
#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_CNT_REG \
    (CSR_DFX_GLB_CSR_BASE + 0x6B8) /* the result for the window detect for the mode */
#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_TLP_CNT_REG \
    (CSR_DFX_GLB_CSR_BASE + 0x6BC) /* the result for the window detect for the TLP */
#define CSR_DFX_GLB_CSR_GLB_DBG_CNT_DBL_GRP_EN_REG (CSR_DFX_GLB_CSR_BASE + 0x6C0)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_TIMER_CFG_REG (CSR_DFX_GLB_CSR_BASE + 0x6C4)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CFG_PORT01_REG (CSR_DFX_GLB_CSR_BASE + 0x6C8)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CFG_PORT23_REG (CSR_DFX_GLB_CSR_BASE + 0x6CC)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT0_REG (CSR_DFX_GLB_CSR_BASE + 0x6D0)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT1_REG (CSR_DFX_GLB_CSR_BASE + 0x6D4)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT2_REG (CSR_DFX_GLB_CSR_BASE + 0x6D8)
#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT3_REG (CSR_DFX_GLB_CSR_BASE + 0x6DC)
#define CSR_DFX_GLB_CSR_CPATH_ENJ_A_FATAL_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x700)
#define CSR_DFX_GLB_CSR_CPATH_ENJ_A_NONFATAL_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x704)
#define CSR_DFX_GLB_CSR_CPATH_ENJ_FIFO_AFUL_TH_REG (CSR_DFX_GLB_CSR_BASE + 0x708)
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x710)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x714)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT2_REG (CSR_DFX_GLB_CSR_BASE + 0x718)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT3_REG (CSR_DFX_GLB_CSR_BASE + 0x71C)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT4_REG (CSR_DFX_GLB_CSR_BASE + 0x720)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT5_REG (CSR_DFX_GLB_CSR_BASE + 0x724)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT6_REG (CSR_DFX_GLB_CSR_BASE + 0x728)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT7_REG (CSR_DFX_GLB_CSR_BASE + 0x72C)  /* CPATH_ENJ模块的dfx寄存器 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO0_REG (CSR_DFX_GLB_CSR_BASE + 0x730) /* CPATH内下RING FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO1_REG (CSR_DFX_GLB_CSR_BASE + 0x734) /* CPATH内下RING FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO2_REG (CSR_DFX_GLB_CSR_BASE + 0x738) /* CPATH内上RING FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO3_REG \
    (CSR_DFX_GLB_CSR_BASE + 0x73C) /* CPATH内ICPL返回完成包接口FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO4_REG (CSR_DFX_GLB_CSR_BASE + 0x740) /* CPATH内FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO5_REG (CSR_DFX_GLB_CSR_BASE + 0x744) /* CPATH内FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO6_REG (CSR_DFX_GLB_CSR_BASE + 0x748) /* CPATH内FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO7_REG (CSR_DFX_GLB_CSR_BASE + 0x74C) /* CPATH内FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO8_REG (CSR_DFX_GLB_CSR_BASE + 0x750) /* CPATH内FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO9_REG (CSR_DFX_GLB_CSR_BASE + 0x754) /* CPATH内FIFO状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO0_REG (CSR_DFX_GLB_CSR_BASE + 0x758)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO1_REG (CSR_DFX_GLB_CSR_BASE + 0x75C)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO2_REG (CSR_DFX_GLB_CSR_BASE + 0x760)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO3_REG (CSR_DFX_GLB_CSR_BASE + 0x764)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO4_REG (CSR_DFX_GLB_CSR_BASE + 0x768)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO5_REG (CSR_DFX_GLB_CSR_BASE + 0x76C)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO6_REG (CSR_DFX_GLB_CSR_BASE + 0x770)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO7_REG (CSR_DFX_GLB_CSR_BASE + 0x774)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO8_REG (CSR_DFX_GLB_CSR_BASE + 0x778)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO9_REG (CSR_DFX_GLB_CSR_BASE + 0x77C)       /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO10_REG (CSR_DFX_GLB_CSR_BASE + 0x780)      /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO11_REG (CSR_DFX_GLB_CSR_BASE + 0x784)      /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO12_REG (CSR_DFX_GLB_CSR_BASE + 0x788)      /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO13_REG (CSR_DFX_GLB_CSR_BASE + 0x78C)      /* CPATH内实时状态 */
#define CSR_DFX_GLB_CSR_CPATH_ENJ_PLS_REG (CSR_DFX_GLB_CSR_BASE + 0x7A0)
#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS0_REG (CSR_DFX_GLB_CSR_BASE + 0x7B0)  /* ctrl_bus配置值，软件不要改。 */
#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS1_REG (CSR_DFX_GLB_CSR_BASE + 0x7B4)  /* ctrl_bus配置值，软件不要改。 */
#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS2_REG (CSR_DFX_GLB_CSR_BASE + 0x7B8)  /* ctrl_bus配置值，软件不要改。 */
#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS3_REG (CSR_DFX_GLB_CSR_BASE + 0x7BC)  /* ctrl_bus配置值，软件不要改。 */
#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS4_REG (CSR_DFX_GLB_CSR_BASE + 0x7C0)  /* ctrl_bus配置值，软件不要改。 */
#define CSR_DFX_GLB_CSR_CTRL_TCAM_CTRL_BUS0_REG (CSR_DFX_GLB_CSR_BASE + 0x7C4) /* ctrl_bus配置值，软件不要改。 */

/* dfx_ctrl_top_csr Base address of Module's Register */
#define CSR_DFX_CTRL_TOP_CSR_BASE (0x43AF800)

/* **************************************************************************** */
/*                      dfx_ctrl_top_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x0)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_ARB_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x8)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x10)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x14)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x18)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x20)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x24)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x28)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x30)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x34)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x38)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_12_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x3C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_13_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x40)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_14_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x44)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_15_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x48)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_16_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_17_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x50)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_18_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x54)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_19_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x58)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_20_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x5C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_21_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x60)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_22_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x64)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_23_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x68)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_24_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_25_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x70)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_26_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x74)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_27_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x78)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_28_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x7C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_29_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x80)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_30_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x84)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_31_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x88)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_32_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x8C)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_33_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x90)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_34_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x94)
#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA0)
#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA4)
#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA8)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO0_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB0)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO1_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB4)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO2_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB8)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO3_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xBC)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO4_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC0)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO5_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC4)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO6_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC8)
#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO7_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xCC)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_FIFO_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x100)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_ARB_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x108)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x110)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x114)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x118)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x11C)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x120)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x124)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x128)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x12C)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x130)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x134)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x138)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x13C)
#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x150)
#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x154)
#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x158)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_RO_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x180)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_RO_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x184)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_20_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x198)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_21_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x19C)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A4)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A8)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1AC)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B4)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B8)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1BC)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C4)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C8)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1CC)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_12_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_13_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D4)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_14_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D8)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_15_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1DC)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_16_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_17_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E4)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_18_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E8)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_19_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1EC)
#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F0)
#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F4)
#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F8)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x200)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x204)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x208)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x20C)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x210)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x214)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x218)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x21C)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x220)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x224)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x228)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x22C)
#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_FIFO_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x280)
#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_FIFO_STS_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x290)
#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_STS_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x294)
#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A0)
#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A4)
#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A8)
#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_WEIGHT_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x400)
#define CSR_DFX_CTRL_TOP_CSR_OSCH_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x404)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x408)
#define CSR_DFX_CTRL_TOP_CSR_DWQE_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x40C)
#define CSR_DFX_CTRL_TOP_CSR_QMAP_TCAM_RSVD_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x410)
#define CSR_DFX_CTRL_TOP_CSR_NVME_DB_COS_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x440)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DB_COS_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x444)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x448)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CFG_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x44C)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_STS0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x490)
#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_DLY_TIMER_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x498)
#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_DLY_TIMER_UNIT_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x49C)
#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_ENABLE_DLY_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4A0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_MCTP_RX_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4B0)
#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_PCIE_ITF_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4B4)
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_RSVD_Q_CFG_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x500) /* VIRTIO缺省队列配置 */
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_RSVD_Q_CFG_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x504) /* VIRTIO缺省队列配置 */
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_CFG0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A0)  /* 三网合一功能的cos配置 */
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_CFG1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A4)  /* 三网合一功能的cos配置 */
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_RP_EN_ALL_REG \
    (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A8) /* 三网合一时替换使能cos功能 */
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DIRECT_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6AC) /* 将满水线DFX */
#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_API_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6B0)    /* 将满水线DFX */

/* dfx_cpath_csr Base address of Module's Register */
#define CSR_DFX_CPATH_CSR_BASE (0x43B0800)

/* **************************************************************************** */
/*                      dfx_cpath_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_DFX_CPATH_CSR_CPATH_CSR_INJ_ENJ_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x10)
#define CSR_DFX_CPATH_CSR_CPATH_INBD_INJ_ENJ_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x14)
#define CSR_DFX_CPATH_CSR_CPATH_NON_CPI_INT_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x1C)
#define CSR_DFX_CPATH_CSR_CPATH_ENJ_RSVD_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x20)
#define CSR_DFX_CPATH_CSR_CPATH_ENJ_NML_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x24)
#define CSR_DFX_CPATH_CSR_CPATH_INBD_OUBD_CNT_TYPE_REG (CSR_DFX_CPATH_CSR_BASE + 0x2C)
#define CSR_DFX_CPATH_CSR_CPATH_FIFO_AFUL_GAP_0_REG (CSR_DFX_CPATH_CSR_BASE + 0x30)
#define CSR_DFX_CPATH_CSR_CPATH_RESERVD_REG (CSR_DFX_CPATH_CSR_BASE + 0x3C) /* ECO保留 */
#define CSR_DFX_CPATH_CSR_CPATH_ITF_STS_OUT_REG (CSR_DFX_CPATH_CSR_BASE + 0x44)
#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PE1_REG (CSR_DFX_CPATH_CSR_BASE + 0x4C)
#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PE0_REG (CSR_DFX_CPATH_CSR_BASE + 0x50)
#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PI_REG (CSR_DFX_CPATH_CSR_BASE + 0x54)
#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PE1_REG (CSR_DFX_CPATH_CSR_BASE + 0x58)
#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PE0_REG (CSR_DFX_CPATH_CSR_BASE + 0x5C)
#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PI_REG (CSR_DFX_CPATH_CSR_BASE + 0x60)
#define CSR_DFX_CPATH_CSR_CPATH_OUT_PLS_REG (CSR_DFX_CPATH_CSR_BASE + 0x70)
#define CSR_DFX_CPATH_CSR_GLB_IJT_NODE_ID_BITMAP_REG (CSR_DFX_CPATH_CSR_BASE + 0x80)
#define CSR_DFX_CPATH_CSR_GLB_EJT_NODE_ID_BITMAP_REG (CSR_DFX_CPATH_CSR_BASE + 0x84)
#define CSR_DFX_CPATH_CSR_CPATH_OUT_A_FATAL_MSK_REG (CSR_DFX_CPATH_CSR_BASE + 0x100)
#define CSR_DFX_CPATH_CSR_CPATH_OUT_A_NONFATAL_MSK_REG (CSR_DFX_CPATH_CSR_BASE + 0x104)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK0_REG (CSR_DFX_CPATH_CSR_BASE + 0x110)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK1_REG (CSR_DFX_CPATH_CSR_BASE + 0x114)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK2_REG (CSR_DFX_CPATH_CSR_BASE + 0x118)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK3_REG (CSR_DFX_CPATH_CSR_BASE + 0x11C)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK4_REG (CSR_DFX_CPATH_CSR_BASE + 0x120)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK5_REG (CSR_DFX_CPATH_CSR_BASE + 0x124)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK6_REG (CSR_DFX_CPATH_CSR_BASE + 0x128)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK7_REG (CSR_DFX_CPATH_CSR_BASE + 0x12C)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK8_REG (CSR_DFX_CPATH_CSR_BASE + 0x130)
#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK9_REG (CSR_DFX_CPATH_CSR_BASE + 0x134)

/* dfx_apictl_csr Base address of Module's Register */
#define CSR_DFX_APICTL_CSR_BASE (0x43B2000)

/* **************************************************************************** */
/*                      dfx_apictl_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_DFX_APICTL_CSR_APICTL_DBG_SEL_REG (CSR_DFX_APICTL_CSR_BASE + 0x0)
#define CSR_DFX_APICTL_CSR_APICTL_AF_TH0_REG (CSR_DFX_APICTL_CSR_BASE + 0x4)
#define CSR_DFX_APICTL_CSR_APICTL_AF_TH1_REG (CSR_DFX_APICTL_CSR_BASE + 0x8)
#define CSR_DFX_APICTL_CSR_APICTL_AF_TH2_REG (CSR_DFX_APICTL_CSR_BASE + 0xC)
#define CSR_DFX_APICTL_CSR_APICTL_AF_TH3_REG (CSR_DFX_APICTL_CSR_BASE + 0x10)
#define CSR_DFX_APICTL_CSR_APICTL_CNT2_REG (CSR_DFX_APICTL_CSR_BASE + 0x18)
#define CSR_DFX_APICTL_CSR_APICTL_CNT3_REG (CSR_DFX_APICTL_CSR_BASE + 0x1C)
#define CSR_DFX_APICTL_CSR_APICTL_CNT4_REG (CSR_DFX_APICTL_CSR_BASE + 0x20)
#define CSR_DFX_APICTL_CSR_APICTL_CNT5_REG (CSR_DFX_APICTL_CSR_BASE + 0x24)
#define CSR_DFX_APICTL_CSR_APICTL_CNT6_REG (CSR_DFX_APICTL_CSR_BASE + 0x28)
#define CSR_DFX_APICTL_CSR_APICTL_RESERVD_REG (CSR_DFX_APICTL_CSR_BASE + 0x2C) /* ECO保留 */
#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_PLS_REG (CSR_DFX_APICTL_CSR_BASE + 0x30)
#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_PLS_REG (CSR_DFX_APICTL_CSR_BASE + 0x34)
#define CSR_DFX_APICTL_CSR_APICTL_NON_CSR_TIMER_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x38)
#define CSR_DFX_APICTL_CSR_APICTL_CSR_TIMER_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x3C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_A_REG (CSR_DFX_APICTL_CSR_BASE + 0x40)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_B_REG (CSR_DFX_APICTL_CSR_BASE + 0x44)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_C_REG (CSR_DFX_APICTL_CSR_BASE + 0x48)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_D_REG (CSR_DFX_APICTL_CSR_BASE + 0x4C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_E_REG (CSR_DFX_APICTL_CSR_BASE + 0x50)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_F_REG (CSR_DFX_APICTL_CSR_BASE + 0x54)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_G_REG (CSR_DFX_APICTL_CSR_BASE + 0x58)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_H_REG (CSR_DFX_APICTL_CSR_BASE + 0x5C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_I_REG (CSR_DFX_APICTL_CSR_BASE + 0x60)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_J_REG (CSR_DFX_APICTL_CSR_BASE + 0x64)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_K_REG (CSR_DFX_APICTL_CSR_BASE + 0x68)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_L_REG (CSR_DFX_APICTL_CSR_BASE + 0x6C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_M_REG (CSR_DFX_APICTL_CSR_BASE + 0x70)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_N_REG (CSR_DFX_APICTL_CSR_BASE + 0x74)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_O_REG (CSR_DFX_APICTL_CSR_BASE + 0x78)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_P_REG (CSR_DFX_APICTL_CSR_BASE + 0x7C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Q_REG (CSR_DFX_APICTL_CSR_BASE + 0x80)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_R_REG (CSR_DFX_APICTL_CSR_BASE + 0x84)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_S_REG (CSR_DFX_APICTL_CSR_BASE + 0x88)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_T_REG (CSR_DFX_APICTL_CSR_BASE + 0x8C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_U_REG (CSR_DFX_APICTL_CSR_BASE + 0x90)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_V_REG (CSR_DFX_APICTL_CSR_BASE + 0x94)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_W_REG (CSR_DFX_APICTL_CSR_BASE + 0x98)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_X_REG (CSR_DFX_APICTL_CSR_BASE + 0x9C)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Y_REG (CSR_DFX_APICTL_CSR_BASE + 0xA0)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Z_REG (CSR_DFX_APICTL_CSR_BASE + 0xA4)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_A_REG (CSR_DFX_APICTL_CSR_BASE + 0xB0)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_B_REG (CSR_DFX_APICTL_CSR_BASE + 0xB4)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_C_REG (CSR_DFX_APICTL_CSR_BASE + 0xB8)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_D_REG (CSR_DFX_APICTL_CSR_BASE + 0xBC)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_E_REG (CSR_DFX_APICTL_CSR_BASE + 0xC0)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_F_REG (CSR_DFX_APICTL_CSR_BASE + 0xC4)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_G_REG (CSR_DFX_APICTL_CSR_BASE + 0xC8)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_H_REG (CSR_DFX_APICTL_CSR_BASE + 0xCC)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_I_REG (CSR_DFX_APICTL_CSR_BASE + 0xD0)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_J_REG (CSR_DFX_APICTL_CSR_BASE + 0xD4)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_K_REG (CSR_DFX_APICTL_CSR_BASE + 0xD8)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_L_REG (CSR_DFX_APICTL_CSR_BASE + 0xDC)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_M_REG (CSR_DFX_APICTL_CSR_BASE + 0xE0)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_N_REG (CSR_DFX_APICTL_CSR_BASE + 0xE4)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_O_REG (CSR_DFX_APICTL_CSR_BASE + 0xE8)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_P_REG (CSR_DFX_APICTL_CSR_BASE + 0xEC)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_Q_REG (CSR_DFX_APICTL_CSR_BASE + 0xF0)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_R_REG (CSR_DFX_APICTL_CSR_BASE + 0xF4)
#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_S_REG (CSR_DFX_APICTL_CSR_BASE + 0xF8)
#define CSR_DFX_APICTL_CSR_INBD_RING_BUF_CRDT_REG \
    (CSR_DFX_APICTL_CSR_BASE + 0x108) /* inbound API到uP侧的非bypass ring buffer 信用控制寄存器 */
#define CSR_DFX_APICTL_CSR_INBD_CMD_RD_SO_RO_REG \
    (CSR_DFX_APICTL_CSR_BASE + 0x10C) /* API chain发送到host侧的读写命令SO/RO控制寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_RO_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x110)   /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_RO_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x114)   /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x118)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x11C)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_2_REG (CSR_DFX_APICTL_CSR_BASE + 0x120)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_3_REG (CSR_DFX_APICTL_CSR_BASE + 0x124)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_4_REG (CSR_DFX_APICTL_CSR_BASE + 0x128)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_5_REG (CSR_DFX_APICTL_CSR_BASE + 0x12C)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_6_REG (CSR_DFX_APICTL_CSR_BASE + 0x130)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_7_REG (CSR_DFX_APICTL_CSR_BASE + 0x134)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_8_REG (CSR_DFX_APICTL_CSR_BASE + 0x138)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_9_REG (CSR_DFX_APICTL_CSR_BASE + 0x13C)  /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_10_REG (CSR_DFX_APICTL_CSR_BASE + 0x140) /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_11_REG (CSR_DFX_APICTL_CSR_BASE + 0x144) /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_12_REG (CSR_DFX_APICTL_CSR_BASE + 0x148) /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_13_REG (CSR_DFX_APICTL_CSR_BASE + 0x14C) /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_14_REG (CSR_DFX_APICTL_CSR_BASE + 0x150) /* TILE代理模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_RO_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x180)     /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_RO_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x184)     /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x188)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x18C)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_2_REG (CSR_DFX_APICTL_CSR_BASE + 0x190)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_3_REG (CSR_DFX_APICTL_CSR_BASE + 0x194)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_4_REG (CSR_DFX_APICTL_CSR_BASE + 0x198)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_5_REG (CSR_DFX_APICTL_CSR_BASE + 0x19C)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_6_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A0)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_7_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A4)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_8_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A8)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_9_REG (CSR_DFX_APICTL_CSR_BASE + 0x1AC)    /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_10_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B0)   /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_11_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B4)   /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_12_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B8)   /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_13_REG (CSR_DFX_APICTL_CSR_BASE + 0x1BC)   /* NL2模块DFX寄存器 */
#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_FATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x200)
#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_FATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x204)
#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_NONFATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x210)
#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_NONFATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x214)
#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL0_REG (CSR_DFX_APICTL_CSR_BASE + 0x220) /* api chain权限控制 */
#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL1_REG (CSR_DFX_APICTL_CSR_BASE + 0x224) /* api chain权限控制 */
#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL2_REG (CSR_DFX_APICTL_CSR_BASE + 0x228) /* api chain权限控制 */
#define CSR_DFX_APICTL_CSR_APICTL_TAG_CMP_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x230)
#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT0_REG (CSR_DFX_APICTL_CSR_BASE + 0x240)
#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT1_REG (CSR_DFX_APICTL_CSR_BASE + 0x244)
#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT2_REG (CSR_DFX_APICTL_CSR_BASE + 0x248)
#define CSR_DFX_APICTL_CSR_APIITF_RING_DEST_ILLG_SRC_REG (CSR_DFX_APICTL_CSR_BASE + 0x24C)

/* CPI_DMA_CSR Base address of Module's Register */
#define CSR_CPI_DMA_CSR_BASE (0x43B3000)

/* **************************************************************************** */
/*                      CPI_DMA_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_CPI_DMA_CSR_DMA_INDRECT_CTRL_REG (CSR_CPI_DMA_CSR_BASE + 0x0) /* CPI DMA 中间接访控制寄存器 */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_TIMEOUT_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x4)                                            /* dma Indirect Access Timeout Register。 */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_0_REG (CSR_CPI_DMA_CSR_BASE + 0x8) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_1_REG (CSR_CPI_DMA_CSR_BASE + 0xC) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_2_REG (CSR_CPI_DMA_CSR_BASE + 0x10) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_3_REG (CSR_CPI_DMA_CSR_BASE + 0x14) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_4_REG (CSR_CPI_DMA_CSR_BASE + 0x18) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_5_REG (CSR_CPI_DMA_CSR_BASE + 0x1C) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_6_REG (CSR_CPI_DMA_CSR_BASE + 0x20) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_7_REG (CSR_CPI_DMA_CSR_BASE + 0x24) /* dma Indirect Access Data Register */
#define CSR_CPI_DMA_CSR_CPI_DMA_RAM_TMODE_REG (CSR_CPI_DMA_CSR_BASE + 0x40)  /* CPI internal RAM test mode */
#define CSR_CPI_DMA_CSR_MSI_BAR_OFFSET_REG (CSR_CPI_DMA_CSR_BASE + 0x44)     /* 表示配置MSI bar的偏移。 */
#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x50)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x60)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x70)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x80)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x90)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x54)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x64)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x74)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x84)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x94)    /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x58)   /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x68)   /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x78)   /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x88)   /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x98)   /* PF和端口映射寄存器 */
#define CSR_CPI_DMA_CSR_CEQ_NUM_ACC_WEIGHT_REG (CSR_CPI_DMA_CSR_BASE + 0xB0) /* CEQ 分配RAM访问权重寄存器 */
#define CSR_CPI_DMA_CSR_COPY_EP_2_COS_EN_REG (CSR_CPI_DMA_CSR_BASE + 0xB4)   /* 第五host copyEP到COS 使能寄存器。 */
#define CSR_CPI_DMA_CSR_DMA_ATTR_NUM_REG (CSR_CPI_DMA_CSR_BASE + 0xB8)       /* CPI内DMA属性配置寄存器 */
#define CSR_CPI_DMA_CSR_DMA_CTRL_0_REG (CSR_CPI_DMA_CSR_BASE + 0xBC)         /* DMA控制寄存器 */
#define CSR_CPI_DMA_CSR_DMA_RAM_INIT_REG (CSR_CPI_DMA_CSR_BASE + 0xC0)       /* DMA侧ram初始化寄存器 */
#define CSR_CPI_DMA_CSR_DMA_RAM_STATUS_REG (CSR_CPI_DMA_CSR_BASE + 0xC4)     /* DMA侧ram初始化状态寄存器 */
#define CSR_CPI_DMA_CSR_PCIE_TIMEOUT_REG (CSR_CPI_DMA_CSR_BASE + 0xD0)       /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_PCIE_TAG_FORCE_REG (CSR_CPI_DMA_CSR_BASE + 0xD4)     /* 强制回收某PF/VF的读命令 */
#define CSR_CPI_DMA_CSR_PCIE_TAG_FORCE_ITF_REG (CSR_CPI_DMA_CSR_BASE + 0xD8) /* 强制回收某PCIe端口的读命令 */
#define CSR_CPI_DMA_CSR_TIMEOUT_DLY_CFG_REG (CSR_CPI_DMA_CSR_BASE + 0xDC)    /* 配置超时tag重复利用的静默时间 */
#define CSR_CPI_DMA_CSR_PCIE_CFG_MOD_REG (CSR_CPI_DMA_CSR_BASE + 0xE0)       /* 表示CPI使用pcie 配置空间的模式 */
#define CSR_CPI_DMA_CSR_PCIE_CFG_LOC_SET_REG (CSR_CPI_DMA_CSR_BASE + 0xE4)   /* 表示CPI使用pcie 配置空间的模式 */
#define CSR_CPI_DMA_CSR_SPU_CFG_LOC_SET_REG (CSR_CPI_DMA_CSR_BASE + 0xE8)    /* 表示CPI使用SPU侧pcie 配置空间的模式 */
#define CSR_CPI_DMA_CSR_DMA_TOP_ECO0_REG (CSR_CPI_DMA_CSR_BASE + 0xEC)       /* DMATOP保留寄存器 */
#define CSR_CPI_DMA_CSR_DMA_TOP_ECO1_REG (CSR_CPI_DMA_CSR_BASE + 0xF0)       /* DMATOP保留寄存器 */
#define CSR_CPI_DMA_CSR_DMA_TOP_ECO2_REG (CSR_CPI_DMA_CSR_BASE + 0xF4)       /* DMATOP保留寄存器 */
#define CSR_CPI_DMA_CSR_DMA_TOP_ECO3_REG (CSR_CPI_DMA_CSR_BASE + 0xF8)       /* DMATOP保留寄存器 */
#define CSR_CPI_DMA_CSR_DMA_TOP_ECO4_REG (CSR_CPI_DMA_CSR_BASE + 0xFC)       /* DMATOP保留寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_0_REG (CSR_CPI_DMA_CSR_BASE + 0x100)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_1_REG (CSR_CPI_DMA_CSR_BASE + 0x120)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_2_REG (CSR_CPI_DMA_CSR_BASE + 0x140)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_3_REG (CSR_CPI_DMA_CSR_BASE + 0x160)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_4_REG (CSR_CPI_DMA_CSR_BASE + 0x180)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_0_REG (CSR_CPI_DMA_CSR_BASE + 0x104)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_1_REG (CSR_CPI_DMA_CSR_BASE + 0x124)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_2_REG (CSR_CPI_DMA_CSR_BASE + 0x144)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_3_REG (CSR_CPI_DMA_CSR_BASE + 0x164)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_4_REG (CSR_CPI_DMA_CSR_BASE + 0x184)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_0_REG (CSR_CPI_DMA_CSR_BASE + 0x108)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_1_REG (CSR_CPI_DMA_CSR_BASE + 0x128)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_2_REG (CSR_CPI_DMA_CSR_BASE + 0x148)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_3_REG (CSR_CPI_DMA_CSR_BASE + 0x168)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_4_REG (CSR_CPI_DMA_CSR_BASE + 0x188)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_0_REG (CSR_CPI_DMA_CSR_BASE + 0x10C)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_1_REG (CSR_CPI_DMA_CSR_BASE + 0x12C)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_2_REG (CSR_CPI_DMA_CSR_BASE + 0x14C)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_3_REG (CSR_CPI_DMA_CSR_BASE + 0x16C)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_4_REG (CSR_CPI_DMA_CSR_BASE + 0x18C)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_0_REG (CSR_CPI_DMA_CSR_BASE + 0x110)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_1_REG (CSR_CPI_DMA_CSR_BASE + 0x130)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_2_REG (CSR_CPI_DMA_CSR_BASE + 0x150)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_3_REG (CSR_CPI_DMA_CSR_BASE + 0x170)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_4_REG (CSR_CPI_DMA_CSR_BASE + 0x190)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_0_REG (CSR_CPI_DMA_CSR_BASE + 0x114)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_1_REG (CSR_CPI_DMA_CSR_BASE + 0x134)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_2_REG (CSR_CPI_DMA_CSR_BASE + 0x154)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_3_REG (CSR_CPI_DMA_CSR_BASE + 0x174)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_4_REG (CSR_CPI_DMA_CSR_BASE + 0x194)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_0_REG (CSR_CPI_DMA_CSR_BASE + 0x118)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_1_REG (CSR_CPI_DMA_CSR_BASE + 0x138)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_2_REG (CSR_CPI_DMA_CSR_BASE + 0x158)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_3_REG (CSR_CPI_DMA_CSR_BASE + 0x178)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_4_REG (CSR_CPI_DMA_CSR_BASE + 0x198)    /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_0_REG (CSR_CPI_DMA_CSR_BASE + 0x11C) /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_1_REG (CSR_CPI_DMA_CSR_BASE + 0x13C) /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_2_REG (CSR_CPI_DMA_CSR_BASE + 0x15C) /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_3_REG (CSR_CPI_DMA_CSR_BASE + 0x17C) /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_4_REG (CSR_CPI_DMA_CSR_BASE + 0x19C) /* CPI发送读命令超时配置寄存器 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT0_REG (CSR_CPI_DMA_CSR_BASE + 0x240)            /* PDI 模块统计计数器0 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT1_REG (CSR_CPI_DMA_CSR_BASE + 0x244)            /* PDI 模块统计计数器1 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT2_REG (CSR_CPI_DMA_CSR_BASE + 0x248)            /* PDI 模块统计计数器2 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT3_REG (CSR_CPI_DMA_CSR_BASE + 0x24C)            /* PDI 模块统计计数器3 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT4_REG (CSR_CPI_DMA_CSR_BASE + 0x250)            /* PDI 模块统计计数器4 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT5_REG (CSR_CPI_DMA_CSR_BASE + 0x254)            /* PDI 模块统计计数器5 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT6_REG (CSR_CPI_DMA_CSR_BASE + 0x258)            /* PDI 模块统计计数器1 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT7_REG (CSR_CPI_DMA_CSR_BASE + 0x25C)            /* PDI 模块统计计数器1 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT8_REG (CSR_CPI_DMA_CSR_BASE + 0x260)            /* PDI 模块统计计数器1 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT9_REG (CSR_CPI_DMA_CSR_BASE + 0x264)            /* PDI 模块统计计数器2 */
#define CSR_CPI_DMA_CSR_PDI_TAG_CNT10_REG (CSR_CPI_DMA_CSR_BASE + 0x268)           /* PDI 模块统计计数器2 */
#define CSR_CPI_DMA_CSR_CEQ_BLK_CNT_REG (CSR_CPI_DMA_CSR_BASE + 0x2A0)             /* CEQ 模块统计计数器 */
#define CSR_CPI_DMA_CSR_CEQ_CSR_ST_REG (CSR_CPI_DMA_CSR_BASE + 0x2A4)              /* CEQ 模块各状态寄存器 */
#define CSR_CPI_DMA_CSR_FLR_RCV_CNT0_REG (CSR_CPI_DMA_CSR_BASE + 0x2B0)            /* CPI接收FLR统计计数器 */
#define CSR_CPI_DMA_CSR_FLR_RCV_CNT1_REG (CSR_CPI_DMA_CSR_BASE + 0x2B4)            /* CPI接收FLR统计计数器 */
#define CSR_CPI_DMA_CSR_FLR_RCV_CNT2_REG (CSR_CPI_DMA_CSR_BASE + 0x2B8)            /* CPI接收FLR统计计数器 */
#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS0_REG (CSR_CPI_DMA_CSR_BASE + 0x2E0)           /* CTRL_BUS值，软件不要改 */
#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS1_REG (CSR_CPI_DMA_CSR_BASE + 0x2E4)           /* CTRL_BUS值，软件不要改 */
#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS2_REG (CSR_CPI_DMA_CSR_BASE + 0x2E8)           /* CTRL_BUS值，软件不要改 */
#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS3_REG (CSR_CPI_DMA_CSR_BASE + 0x2EC)           /* CTRL_BUS值，软件不要改 */
#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS4_REG (CSR_CPI_DMA_CSR_BASE + 0x2F0)           /* CTRL_BUS值，软件不要改 */
#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_CTL_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x300) /* the control register to measure the inbound itf */
#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_CNT_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x304) /* the result for the window detect for the mode */
#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_TLP_CNT_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x308) /* the result for the window detect for the TLP */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_0_REG (CSR_CPI_DMA_CSR_BASE + 0x340)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_1_REG (CSR_CPI_DMA_CSR_BASE + 0x344)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_2_REG (CSR_CPI_DMA_CSR_BASE + 0x348)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_3_REG (CSR_CPI_DMA_CSR_BASE + 0x34C)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_4_REG (CSR_CPI_DMA_CSR_BASE + 0x350)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_5_REG (CSR_CPI_DMA_CSR_BASE + 0x354)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_6_REG (CSR_CPI_DMA_CSR_BASE + 0x358)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_7_REG (CSR_CPI_DMA_CSR_BASE + 0x35C)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_8_REG (CSR_CPI_DMA_CSR_BASE + 0x360)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_9_REG (CSR_CPI_DMA_CSR_BASE + 0x364)   /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_10_REG (CSR_CPI_DMA_CSR_BASE + 0x368)  /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_11_REG (CSR_CPI_DMA_CSR_BASE + 0x36C)  /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_12_REG (CSR_CPI_DMA_CSR_BASE + 0x370)  /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_13_REG (CSR_CPI_DMA_CSR_BASE + 0x374)  /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_14_REG (CSR_CPI_DMA_CSR_BASE + 0x378)  /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_15_REG (CSR_CPI_DMA_CSR_BASE + 0x37C)  /* CPI Recive the bme clear cfg */
#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_SEL_REG (CSR_CPI_DMA_CSR_BASE + 0x380) /* select the tag timeout funciton */
#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_CLEAR_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x384) /* clear the selected funciton tag timeout */
#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_ST_OUT_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x388) /* read the selected funciton tag timeout */
#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_GROUP_ST_OUT_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x38C) /* read the selected funciton tag timeout */
#define CSR_CPI_DMA_CSR_CPI_PDI_A_FATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3E0)    /* PDI模块中断级别配置寄存器 */
#define CSR_CPI_DMA_CSR_CPI_PDI_A_NONFATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3E4) /* PDI模块中断级别配置寄存器 */
#define CSR_CPI_DMA_CSR_CPI_PDI_A_INT_PLS_REG (CSR_CPI_DMA_CSR_BASE + 0x3E8)      /* PDI模块中断状态寄存器 */
#define CSR_CPI_DMA_CSR_CPI_PDI_B_FATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3F0)    /* PDI模块中断级别配置寄存器 */
#define CSR_CPI_DMA_CSR_CPI_PDI_B_NONFATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3F4) /* PDI模块中断级别配置寄存器 */
#define CSR_CPI_DMA_CSR_CPI_PDI_B_INT_PLS_REG (CSR_CPI_DMA_CSR_BASE + 0x3F8)      /* PDI模块中断状态寄存器 */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_0_REG (CSR_CPI_DMA_CSR_BASE + 0x400)    /* the enable for virtio capability */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_1_REG (CSR_CPI_DMA_CSR_BASE + 0x404)    /* the enable for virtio capability */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_127_REG (CSR_CPI_DMA_CSR_BASE + 0x5FC)  /* the enable for virtio capability \
                                                                                   */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_00VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x600) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_01VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x604) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_02VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x608) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_03VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x60C) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_04VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x610) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_05VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x614) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_06VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x618) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_07VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x61C) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_08VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x620) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_09VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x630) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_10VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x634) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_11VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x638) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_12VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x63C) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_13VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x640) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_14VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x644) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_15VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x648) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_16VALUE_PF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x64C) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_00VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x680) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_01VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x684) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_02VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x688) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_03VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x68C) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_04VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x690) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_05VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x694) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_06VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x698) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_07VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x69C) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_08VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6A0) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_09VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6B0) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_10VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6B4) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_11VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6B8) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_12VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6BC) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_13VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6C0) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_14VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6C4) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_15VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6C8) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_16VALUE_VF_REG \
    (CSR_CPI_DMA_CSR_BASE + 0x6CC) /* the virtio Capability for VirtIO */
#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ECC_CERR_REG (CSR_CPI_DMA_CSR_BASE + 0x700)
#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ECC_UCERR_REG (CSR_CPI_DMA_CSR_BASE + 0x704)
#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ERR_ADDR_REG (CSR_CPI_DMA_CSR_BASE + 0x708)
#define CSR_CPI_DMA_CSR_DMATOP_ECC_INJ_REQ_REG (CSR_CPI_DMA_CSR_BASE + 0x710)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_A_REG (CSR_CPI_DMA_CSR_BASE + 0x720)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_B_REG (CSR_CPI_DMA_CSR_BASE + 0x724)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_C_REG (CSR_CPI_DMA_CSR_BASE + 0x728)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_D_REG (CSR_CPI_DMA_CSR_BASE + 0x72C)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_E_REG (CSR_CPI_DMA_CSR_BASE + 0x730)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_F_REG (CSR_CPI_DMA_CSR_BASE + 0x734)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_G_REG (CSR_CPI_DMA_CSR_BASE + 0x738)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_H_REG (CSR_CPI_DMA_CSR_BASE + 0x73C)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_I_REG (CSR_CPI_DMA_CSR_BASE + 0x740)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_J_REG (CSR_CPI_DMA_CSR_BASE + 0x744)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_K_REG (CSR_CPI_DMA_CSR_BASE + 0x748)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_L_REG (CSR_CPI_DMA_CSR_BASE + 0x74C)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_M_REG (CSR_CPI_DMA_CSR_BASE + 0x750)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_N_REG (CSR_CPI_DMA_CSR_BASE + 0x754)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_O_REG (CSR_CPI_DMA_CSR_BASE + 0x758)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_P_REG (CSR_CPI_DMA_CSR_BASE + 0x75C)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_Q_REG (CSR_CPI_DMA_CSR_BASE + 0x760)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_R_REG (CSR_CPI_DMA_CSR_BASE + 0x764)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_S_REG (CSR_CPI_DMA_CSR_BASE + 0x768)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_T_REG (CSR_CPI_DMA_CSR_BASE + 0x76C)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_U_REG (CSR_CPI_DMA_CSR_BASE + 0x770)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_A_REG (CSR_CPI_DMA_CSR_BASE + 0x780)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_B_REG (CSR_CPI_DMA_CSR_BASE + 0x784)
#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_C_REG (CSR_CPI_DMA_CSR_BASE + 0x788)

/* CPI_ICPL_CSR Base address of Module's Register */
#define CSR_CPI_ICPL_CSR_BASE (0x43B3800)

/* **************************************************************************** */
/*                      CPI_ICPL_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_CPI_ICPL_CSR_DP_NORMAL_CHL_EN_REG (CSR_CPI_ICPL_CSR_BASE + 0x0) /* 表示dpath普通channel使能寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_RAM_INIT_REG (CSR_CPI_ICPL_CSR_BASE + 0x44)   /* DMA侧ram初始化寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_RAM_STATUS_REG (CSR_CPI_ICPL_CSR_BASE + 0x48) /* DMA侧ram初始化状态寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_FIFO_AFUL_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x50)
#define CSR_CPI_ICPL_CSR_ICPL_FIFO_AFUL_CTL1_REG (CSR_CPI_ICPL_CSR_BASE + 0x54)
#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x100)  /* 当前PCIe 端口分配TAG资源 */
#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x120)  /* 当前PCIe 端口分配TAG资源 */
#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x140)  /* 当前PCIe 端口分配TAG资源 */
#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x160)  /* 当前PCIe 端口分配TAG资源 */
#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x180)  /* 当前PCIe 端口分配TAG资源 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x104)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x124)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x144)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x164)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x184)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x108)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x128)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x148)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x168)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x188)  /* 当前PCIe端口占用的TAG 数目 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x10C) /* 表示PCIe端口内TAG 最大值 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x12C) /* 表示PCIe端口内TAG 最大值 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x14C) /* 表示PCIe端口内TAG 最大值 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x16C) /* 表示PCIe端口内TAG 最大值 */
#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x18C) /* 表示PCIe端口内TAG 最大值 */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_0_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x110) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_1_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x130) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_2_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x150) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_3_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x170) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_4_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x190) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_0_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x114) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_1_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x134) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_2_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x154) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_3_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x174) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_4_REG \
    (CSR_CPI_ICPL_CSR_BASE + 0x194) /* The reorder buffer configuration in the I_CPL */
#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT0_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A0) /* ICPL内仲裁权重寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT1_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A4) /* ICPL内仲裁权重寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT2_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A8) /* ICPL内仲裁权重寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_CTRL_MOD_REG (CSR_CPI_ICPL_CSR_BASE + 0x1AC)    /* ICPL内模式配置就存起 */
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_SEL_REG (CSR_CPI_ICPL_CSR_BASE + 0x300)
#define CSR_CPI_ICPL_CSR_ICPL_RTT_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x304)      /* ICPL控制测量RTT的控制寄存器 */
#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX0_REG (CSR_CPI_ICPL_CSR_BASE + 0x308) /* ICPL用于配置待测量的TAG 编号0。 */
#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX1_REG (CSR_CPI_ICPL_CSR_BASE + 0x30C) /* ICPL用于配置待测量的TAG 编号1。 */
#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX2_REG (CSR_CPI_ICPL_CSR_BASE + 0x310) /* ICPL用于配置待测量的TAG 编号2。 */
#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x314) /* ICPL用于测量RTT范围的控制寄存器。 */
#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG1_REG (CSR_CPI_ICPL_CSR_BASE + 0x318)
#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG2_REG (CSR_CPI_ICPL_CSR_BASE + 0x31C)
#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG3_REG (CSR_CPI_ICPL_CSR_BASE + 0x320)
#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG4_REG (CSR_CPI_ICPL_CSR_BASE + 0x324)
#define CSR_CPI_ICPL_CSR_ICPL_RTT_CUR_REG (CSR_CPI_ICPL_CSR_BASE + 0x328)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_A_REG (CSR_CPI_ICPL_CSR_BASE + 0x360)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_B_REG (CSR_CPI_ICPL_CSR_BASE + 0x364)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_C_REG (CSR_CPI_ICPL_CSR_BASE + 0x368)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_D_REG (CSR_CPI_ICPL_CSR_BASE + 0x36C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_E_REG (CSR_CPI_ICPL_CSR_BASE + 0x370)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_F_REG (CSR_CPI_ICPL_CSR_BASE + 0x374)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_G_REG (CSR_CPI_ICPL_CSR_BASE + 0x378)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_H_REG (CSR_CPI_ICPL_CSR_BASE + 0x37C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_I_REG (CSR_CPI_ICPL_CSR_BASE + 0x380)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_J_REG (CSR_CPI_ICPL_CSR_BASE + 0x384)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_K_REG (CSR_CPI_ICPL_CSR_BASE + 0x388)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_L_REG (CSR_CPI_ICPL_CSR_BASE + 0x38C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_M_REG (CSR_CPI_ICPL_CSR_BASE + 0x390)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_N_REG (CSR_CPI_ICPL_CSR_BASE + 0x394)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_O_REG (CSR_CPI_ICPL_CSR_BASE + 0x398)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_P_REG (CSR_CPI_ICPL_CSR_BASE + 0x39C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Q_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A0)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_R_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A4)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_S_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A8)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_T_REG (CSR_CPI_ICPL_CSR_BASE + 0x3AC)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_U_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B0)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_V_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B4)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_W_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B8)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_X_REG (CSR_CPI_ICPL_CSR_BASE + 0x3BC)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Y_REG (CSR_CPI_ICPL_CSR_BASE + 0x3C0)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Z_REG (CSR_CPI_ICPL_CSR_BASE + 0x3C4)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x400)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x410)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x420)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x430)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x440)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x450)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x460)
#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x470)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x408)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x418)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x428)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x438)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x448)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x458)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x468)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x478)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x40C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x41C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x42C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x43C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x44C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x45C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x46C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x47C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT2_REG (CSR_CPI_ICPL_CSR_BASE + 0x480)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT3_REG (CSR_CPI_ICPL_CSR_BASE + 0x484)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT4_REG (CSR_CPI_ICPL_CSR_BASE + 0x488)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT5_REG (CSR_CPI_ICPL_CSR_BASE + 0x48C)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x490)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x494)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x498)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x49C)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A0)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A4)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A8)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x4AC)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_8_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B0)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_9_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B4)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_10_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B8)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_11_REG (CSR_CPI_ICPL_CSR_BASE + 0x4BC)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_12_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C0)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_13_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C4)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_14_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C8)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_15_REG (CSR_CPI_ICPL_CSR_BASE + 0x4CC)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_16_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D0)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_17_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D4)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_18_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D8)
#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_19_REG (CSR_CPI_ICPL_CSR_BASE + 0x4DC)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_A_REG (CSR_CPI_ICPL_CSR_BASE + 0x500)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_B_REG (CSR_CPI_ICPL_CSR_BASE + 0x504)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_C_REG (CSR_CPI_ICPL_CSR_BASE + 0x508)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_D_REG (CSR_CPI_ICPL_CSR_BASE + 0x50C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_E_REG (CSR_CPI_ICPL_CSR_BASE + 0x510)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_F_REG (CSR_CPI_ICPL_CSR_BASE + 0x514)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_G_REG (CSR_CPI_ICPL_CSR_BASE + 0x518)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_H_REG (CSR_CPI_ICPL_CSR_BASE + 0x51C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_I_REG (CSR_CPI_ICPL_CSR_BASE + 0x520)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_J_REG (CSR_CPI_ICPL_CSR_BASE + 0x524)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_K_REG (CSR_CPI_ICPL_CSR_BASE + 0x528)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_L_REG (CSR_CPI_ICPL_CSR_BASE + 0x52C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_M_REG (CSR_CPI_ICPL_CSR_BASE + 0x530)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_N_REG (CSR_CPI_ICPL_CSR_BASE + 0x534)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_O_REG (CSR_CPI_ICPL_CSR_BASE + 0x538)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_P_REG (CSR_CPI_ICPL_CSR_BASE + 0x53C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_Q_REG (CSR_CPI_ICPL_CSR_BASE + 0x540)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_R_REG (CSR_CPI_ICPL_CSR_BASE + 0x544)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_S_REG (CSR_CPI_ICPL_CSR_BASE + 0x548)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_T_REG (CSR_CPI_ICPL_CSR_BASE + 0x54C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_U_REG (CSR_CPI_ICPL_CSR_BASE + 0x550)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_V_REG (CSR_CPI_ICPL_CSR_BASE + 0x554)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_W_REG (CSR_CPI_ICPL_CSR_BASE + 0x558)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_X_REG (CSR_CPI_ICPL_CSR_BASE + 0x55C)
#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_Y_REG (CSR_CPI_ICPL_CSR_BASE + 0x560)
#define CSR_CPI_ICPL_CSR_ICPL_PLSA_FATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E0)
#define CSR_CPI_ICPL_CSR_ICPL_PLSA_NONFATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E4)
#define CSR_CPI_ICPL_CSR_ICPL_PLSA_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E8)
#define CSR_CPI_ICPL_CSR_ICPL_PLSB_FATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F0)
#define CSR_CPI_ICPL_CSR_ICPL_PLSB_NONFATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F4)
#define CSR_CPI_ICPL_CSR_ICPL_PLSB_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F8)
#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ECC_CERR_REG (CSR_CPI_ICPL_CSR_BASE + 0x600)
#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ECC_UCERR_REG (CSR_CPI_ICPL_CSR_BASE + 0x604)
#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ERR_ADDR_REG (CSR_CPI_ICPL_CSR_BASE + 0x608)
#define CSR_CPI_ICPL_CSR_ICPL_ECC_INJ_REQ_REG (CSR_CPI_ICPL_CSR_BASE + 0x610)

/* CPI_INTCTL_CSR Base address of Module's Register */
#define CSR_CPI_INTCTL_CSR_BASE (0x43B4000)

/* **************************************************************************** */
/*                      CPI_INTCTL_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_CPI_INTCTL_CSR_INTCTL_INT_CTL_REG (CSR_CPI_INTCTL_CSR_BASE + 0x0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_BITMAP_REG (CSR_CPI_INTCTL_CSR_BASE + 0x8)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_BITMAP_WNDW_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_AB_REG (CSR_CPI_INTCTL_CSR_BASE + 0x10)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_CD_REG (CSR_CPI_INTCTL_CSR_BASE + 0x14)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_EF_REG (CSR_CPI_INTCTL_CSR_BASE + 0x18)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_GH_REG (CSR_CPI_INTCTL_CSR_BASE + 0x1C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_AB_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x20)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_CD_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x24)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_EF_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x28)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_GH_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_IPUSH_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x30)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_CFG_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x34)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSK_TRIG_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x38)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_COAL_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x3C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_COAL_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x40)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSI_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x44)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSIX_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x48)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_VCT_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x4C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_ASSERT_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x50)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_ASSERT_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x54)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_DEASSERT_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x58)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_DEASSERT_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x5C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_A_REG (CSR_CPI_INTCTL_CSR_BASE + 0x60)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_B_REG (CSR_CPI_INTCTL_CSR_BASE + 0x64)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_C_REG (CSR_CPI_INTCTL_CSR_BASE + 0x68)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_D_REG (CSR_CPI_INTCTL_CSR_BASE + 0x6C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_E_REG (CSR_CPI_INTCTL_CSR_BASE + 0x70)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_F_REG (CSR_CPI_INTCTL_CSR_BASE + 0x74)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_G_REG (CSR_CPI_INTCTL_CSR_BASE + 0x78)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_H_REG (CSR_CPI_INTCTL_CSR_BASE + 0x7C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_I_REG (CSR_CPI_INTCTL_CSR_BASE + 0x80)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_J_REG (CSR_CPI_INTCTL_CSR_BASE + 0x84)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_K_REG (CSR_CPI_INTCTL_CSR_BASE + 0x88)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_L_REG (CSR_CPI_INTCTL_CSR_BASE + 0x8C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_M_REG (CSR_CPI_INTCTL_CSR_BASE + 0x90)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_N_REG (CSR_CPI_INTCTL_CSR_BASE + 0x94)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_O_REG (CSR_CPI_INTCTL_CSR_BASE + 0x98)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x9C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Q_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_R_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_S_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA8)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_T_REG (CSR_CPI_INTCTL_CSR_BASE + 0xAC)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_U_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_V_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_W_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB8)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_X_REG (CSR_CPI_INTCTL_CSR_BASE + 0xBC)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Y_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Z_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_A_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_B_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_C_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD8)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_D_REG (CSR_CPI_INTCTL_CSR_BASE + 0xDC)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_E_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_F_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_G_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE8)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_H_REG (CSR_CPI_INTCTL_CSR_BASE + 0xEC)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_I_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF0)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_J_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_K_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF8)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_L_REG (CSR_CPI_INTCTL_CSR_BASE + 0xFC)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_M_REG (CSR_CPI_INTCTL_CSR_BASE + 0x100)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_N_REG (CSR_CPI_INTCTL_CSR_BASE + 0x104)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_O_REG (CSR_CPI_INTCTL_CSR_BASE + 0x108)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x10C)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_Q_REG (CSR_CPI_INTCTL_CSR_BASE + 0x110)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_R_REG (CSR_CPI_INTCTL_CSR_BASE + 0x114)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_DROP_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x120)
#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x200)
#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_2ND_01P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x204)
#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_2ND_23P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x208)
#define CSR_CPI_INTCTL_CSR_INTCTL_FLR_LIMIT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x220)
#define CSR_CPI_INTCTL_CSR_INTCTL_RESERVD_REG (CSR_CPI_INTCTL_CSR_BASE + 0x230) /* ECO保留 */
#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_A_FATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E0)
#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_A_NONFATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_A_PLUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E8)
#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_B_FATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F0)
#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_B_NONFATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F4)
#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_B_PLUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F8)
#define CSR_CPI_INTCTL_CSR_INTCTL_RAM_INIT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x310)       /* DMA侧ram初始化寄存器 */
#define CSR_CPI_INTCTL_CSR_INTCTL_RAM_STATUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x314)     /* DMA侧ram初始化状态寄存器 */
#define CSR_CPI_INTCTL_CSR_INTCTL_CTL_REG (CSR_CPI_INTCTL_CSR_BASE + 0x318)            /* intctl模块控制寄存器 */
#define CSR_CPI_INTCTL_CSR_INTCTL_RES_REG (CSR_CPI_INTCTL_CSR_BASE + 0x31C)            /* int ctl 资源配置 */
#define CSR_CPI_INTCTL_CSR_INTCTL_CSR_ACC_WEIGHT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x320) /* 中断模块访问权重控制寄存器 \
                                                                                        */
#define CSR_CPI_INTCTL_CSR_INTCTL1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x324)
#define CSR_CPI_INTCTL_CSR_INTCTL2_REG (CSR_CPI_INTCTL_CSR_BASE + 0x328)
#define CSR_CPI_INTCTL_CSR_INTCTL3_REG (CSR_CPI_INTCTL_CSR_BASE + 0x32C)
#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ECC_CERR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x400)
#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ECC_UCERR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x404)
#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ERR_ADDR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x408)
#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_MULTI_ERR_ADDR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x40C)
#define CSR_CPI_INTCTL_CSR_INTCTL_ECC_INJ_REQ_REG (CSR_CPI_INTCTL_CSR_BASE + 0x410)

/* CPI_OCTL_CSR Base address of Module's Register */
#define CSR_CPI_OCTL_CSR_BASE (0x43B4800)

/* **************************************************************************** */
/*                      CPI_OCTL_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_CTRL0_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x0) /* CPI_OCTL internal table indirect access ctrl registers */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_CTRL1_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x4) /* CPI_OCTL internal table indirect access ctrl registers */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_0_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x8) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_1_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0xC) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_2_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x10) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_3_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x14) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_4_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x18) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_5_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x1C) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_6_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x20) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_7_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x24) /* CPI_OCTL internal table indirect access data */
#define CSR_CPI_OCTL_CSR_OCTL_RAM_INIT_REQ_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x28) /* CPI_OCTL internal RAM initial request */
#define CSR_CPI_OCTL_CSR_OCTL_RAM_INIT_STS_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C) /* CPI_OCTL internal RAM initial status \
                                                                               */
#define CSR_CPI_OCTL_CSR_PRE_SUB_DAT_CRD_CPB_REG (CSR_CPI_OCTL_CSR_BASE + 0x30) /* Data Credit presub value from CPB \
                                                                                 */
#define CSR_CPI_OCTL_CSR_L2NIC_CI_WR_CHL_CFG_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x34) /* specifies the D-Path channel for the CI write. */
#define CSR_CPI_OCTL_CSR_CQE_WR_CHL_CFG_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x38) /* specifies the D-Path channel for the CQE write. */
#define CSR_CPI_OCTL_CSR_PCIE_PORT_CFG_REG \
    (CSR_CPI_OCTL_CSR_BASE + 0x3C) /* specifies which PCIe port's FIFO configuration */
#define CSR_CPI_OCTL_CSR_DMA_PE_YYY_FIFO_DEPTH_PORT012_REG (CSR_CPI_OCTL_CSR_BASE + 0x40)
#define CSR_CPI_OCTL_CSR_DMA_PE_YYY_FIFO_DEPTH_PORT34_REG (CSR_CPI_OCTL_CSR_BASE + 0x44)
#define CSR_CPI_OCTL_CSR_CPI_PREALLOC_CPB_BUF_REG (CSR_CPI_OCTL_CSR_BASE + 0x48) /* the pre-alloc CPB buffers */
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x50)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x54)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x58)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x5C)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_5_REG (CSR_CPI_OCTL_CSR_BASE + 0x60)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_6_REG (CSR_CPI_OCTL_CSR_BASE + 0x64)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_7_REG (CSR_CPI_OCTL_CSR_BASE + 0x68)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_8_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_9_REG (CSR_CPI_OCTL_CSR_BASE + 0x70)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_10_REG (CSR_CPI_OCTL_CSR_BASE + 0x74)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_11_REG (CSR_CPI_OCTL_CSR_BASE + 0x78)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_12_REG (CSR_CPI_OCTL_CSR_BASE + 0x7C)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_13_REG (CSR_CPI_OCTL_CSR_BASE + 0x80)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_14_REG (CSR_CPI_OCTL_CSR_BASE + 0x84)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_15_REG (CSR_CPI_OCTL_CSR_BASE + 0x88)
#define CSR_CPI_OCTL_CSR_OCTL_CUT_THR_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x8C)
#define CSR_CPI_OCTL_CSR_OCTL_IN_CMD_CHNL_SRC_SEL_REG (CSR_CPI_OCTL_CSR_BASE + 0x94)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_REG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x98)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_REG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x9C)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0xA0)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0xA4)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_C_REG (CSR_CPI_OCTL_CSR_BASE + 0xA8)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_D_REG (CSR_CPI_OCTL_CSR_BASE + 0xAC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_A_REG (CSR_CPI_OCTL_CSR_BASE + 0xB0)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_B_REG (CSR_CPI_OCTL_CSR_BASE + 0xB4)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_C_REG (CSR_CPI_OCTL_CSR_BASE + 0xB8)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_D_REG (CSR_CPI_OCTL_CSR_BASE + 0xBC)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_E_REG (CSR_CPI_OCTL_CSR_BASE + 0xC0)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_F_REG (CSR_CPI_OCTL_CSR_BASE + 0xC4)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_G_REG (CSR_CPI_OCTL_CSR_BASE + 0xC8)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_H_REG (CSR_CPI_OCTL_CSR_BASE + 0xCC)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_I_REG (CSR_CPI_OCTL_CSR_BASE + 0xD0)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_J_REG (CSR_CPI_OCTL_CSR_BASE + 0xD4)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_K_REG (CSR_CPI_OCTL_CSR_BASE + 0xD8)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_L_REG (CSR_CPI_OCTL_CSR_BASE + 0xDC)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_M_REG (CSR_CPI_OCTL_CSR_BASE + 0xE0)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_N_REG (CSR_CPI_OCTL_CSR_BASE + 0xE4)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_O_REG (CSR_CPI_OCTL_CSR_BASE + 0xE8)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_P_REG (CSR_CPI_OCTL_CSR_BASE + 0xEC)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Q_REG (CSR_CPI_OCTL_CSR_BASE + 0xF0)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_R_REG (CSR_CPI_OCTL_CSR_BASE + 0xF4)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_S_REG (CSR_CPI_OCTL_CSR_BASE + 0xF8)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_T_REG (CSR_CPI_OCTL_CSR_BASE + 0xFC)      /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_U_REG (CSR_CPI_OCTL_CSR_BASE + 0x100)     /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_V_REG (CSR_CPI_OCTL_CSR_BASE + 0x104)     /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_W_REG (CSR_CPI_OCTL_CSR_BASE + 0x108)     /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_X_REG (CSR_CPI_OCTL_CSR_BASE + 0x10C)     /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Y_REG (CSR_CPI_OCTL_CSR_BASE + 0x110)     /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Z_REG (CSR_CPI_OCTL_CSR_BASE + 0x114)     /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x118)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x11C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x120)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x124)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x128)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x12C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x130)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x134)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x138)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x13C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x140)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x144)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x148)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x14C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x150)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x154)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x158)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x15C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AS_REG (CSR_CPI_OCTL_CSR_BASE + 0x160)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AT_REG (CSR_CPI_OCTL_CSR_BASE + 0x164)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AU_REG (CSR_CPI_OCTL_CSR_BASE + 0x168)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AV_REG (CSR_CPI_OCTL_CSR_BASE + 0x16C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AW_REG (CSR_CPI_OCTL_CSR_BASE + 0x170)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AX_REG (CSR_CPI_OCTL_CSR_BASE + 0x174)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AY_REG (CSR_CPI_OCTL_CSR_BASE + 0x178)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AZ_REG (CSR_CPI_OCTL_CSR_BASE + 0x17C)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BA_REG (CSR_CPI_OCTL_CSR_BASE + 0x180)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x184)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BC_REG (CSR_CPI_OCTL_CSR_BASE + 0x188)    /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A0) /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E0) /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x220) /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x260) /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A0) /* CAP */
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x224)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x264)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x228)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x268)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1AC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1EC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x22C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x26C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2AC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x230)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x270)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x234)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x274)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x238)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x278)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1BC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1FC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x23C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x27C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2BC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x200)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x240)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x280)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x204)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x244)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x284)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x208)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x248)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x288)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C8)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1CC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x20C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x24C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x28C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2CC)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1D0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x210)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x250)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x290)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2D0)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1D4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x214)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x254)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x294)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2D4)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BD_REG (CSR_CPI_OCTL_CSR_BASE + 0x300)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BE_REG (CSR_CPI_OCTL_CSR_BASE + 0x304)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BF_REG (CSR_CPI_OCTL_CSR_BASE + 0x308)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BG_REG (CSR_CPI_OCTL_CSR_BASE + 0x30C)
#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BH_REG (CSR_CPI_OCTL_CSR_BASE + 0x310)
#define CSR_CPI_OCTL_CSR_OCTL_DPATH_O_ERR_DFX_REG (CSR_CPI_OCTL_CSR_BASE + 0x340)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BK_REG (CSR_CPI_OCTL_CSR_BASE + 0x350)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BL_REG (CSR_CPI_OCTL_CSR_BASE + 0x354)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x358)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x35C)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x360)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x364)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x368)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x36C)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x370)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x374)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x378)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x37C)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x380)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x384)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x388)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x38C)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x390)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x394)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x398)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x39C)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AS_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A0)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AT_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A4)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AU_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A8)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AV_REG (CSR_CPI_OCTL_CSR_BASE + 0x3AC)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AW_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B0)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AX_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B4)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AY_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B8)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AZ_REG (CSR_CPI_OCTL_CSR_BASE + 0x3BC)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BA_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C0)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C4)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BC_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C8)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BD_REG (CSR_CPI_OCTL_CSR_BASE + 0x3CC)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BE_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D0)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BF_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D4)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BG_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D8)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BH_REG (CSR_CPI_OCTL_CSR_BASE + 0x3DC)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BI_REG (CSR_CPI_OCTL_CSR_BASE + 0x3E0)
#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x3E4)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_BYPASS_REG (CSR_CPI_OCTL_CSR_BASE + 0x3F8)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x3FC)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x400)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x404)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x408)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x40C)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x410)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x414)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x418)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x41C)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x420)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x424)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x428)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x42C)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x430)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x434)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x438)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x43C)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x440)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x444)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x448)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x44C)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x450)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x454)
#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x458)
#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x45C)
#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x460)
#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x464)
#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x468)
#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x46C)
#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x470)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x474)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x478)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x47C)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x480)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x484)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x488)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x48C)
#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x490)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A0)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A4)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A8)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x4AC)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B0)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B4)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B8)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x4BC)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C0)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C4)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C8)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x4CC)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x4D0)
#define CSR_CPI_OCTL_CSR_OCTL_EC_SORO_ATTR_TBL_FIRST_REG (CSR_CPI_OCTL_CSR_BASE + 0x4E4)
#define CSR_CPI_OCTL_CSR_OCTL_EC_SORO_ATTR_TBL_SECOND_REG (CSR_CPI_OCTL_CSR_BASE + 0x4E8)
#define CSR_CPI_OCTL_CSR_OCTL_EC_CHANNEL_ENABLE_REG (CSR_CPI_OCTL_CSR_BASE + 0x4EC)
#define CSR_CPI_OCTL_CSR_OCTL_SM_CBUF_I_READY_CHNL_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F0)
#define CSR_CPI_OCTL_CSR_OCTL_SM_CBUF_I_READY_CHNL_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F4)
#define CSR_CPI_OCTL_CSR_OCTL_MUL_HOST_DIF_RD_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F8)
#define CSR_CPI_OCTL_CSR_OCTL_DB_WR_ADDR_L_REG (CSR_CPI_OCTL_CSR_BASE + 0x4FC)
#define CSR_CPI_OCTL_CSR_OCTL_DB_WR_ADDR_H_REG (CSR_CPI_OCTL_CSR_BASE + 0x500)
#define CSR_CPI_OCTL_CSR_OCTL_ENDIAN_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x504)
#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x560)
#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x564)
#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x568)
#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x56C)
#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x570)
#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x574)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x578)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x57C)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x580)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x584)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x588)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x58C)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_G_REG (CSR_CPI_OCTL_CSR_BASE + 0x590)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_H_REG (CSR_CPI_OCTL_CSR_BASE + 0x594)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x598)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x59C)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A0)
#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A4)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_I_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A8)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_J_REG (CSR_CPI_OCTL_CSR_BASE + 0x5AC)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_K_REG (CSR_CPI_OCTL_CSR_BASE + 0x5B0)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_L_REG (CSR_CPI_OCTL_CSR_BASE + 0x5B4)
#define CSR_CPI_OCTL_CSR_OCTL_PE_PARSER_CFG_1ST_REG (CSR_CPI_OCTL_CSR_BASE + 0x650)
#define CSR_CPI_OCTL_CSR_OCTL_LOOP_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x654)
#define CSR_CPI_OCTL_CSR_OCTL_LOOP_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x658)
#define CSR_CPI_OCTL_CSR_OCTL_DFX_SIG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x65C)
#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x674)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x684)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x694)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6A4)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6B4)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x678)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x688)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x698)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6A8)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6B8)  /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x67C) /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x68C) /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x69C) /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6AC) /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6BC) /* PF和端口映射寄存器 */
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C0)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C4)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C8)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x6CC)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D0)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D4)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D8)
#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x6DC)
#define CSR_CPI_OCTL_CSR_CPI_OCTL_CPATH_CRDT_REG (CSR_CPI_OCTL_CSR_BASE + 0x718) /* CPATH信用配置寄存器 */
#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_ONE_REG (CSR_CPI_OCTL_CSR_BASE + 0x71C)
#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_TWO_REG (CSR_CPI_OCTL_CSR_BASE + 0x720)
#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_THREE_REG (CSR_CPI_OCTL_CSR_BASE + 0x724)
#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_FOUR_REG (CSR_CPI_OCTL_CSR_BASE + 0x728)
#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_FIVE_REG (CSR_CPI_OCTL_CSR_BASE + 0x72C)
#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x730)
#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x734)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_M_REG (CSR_CPI_OCTL_CSR_BASE + 0x738)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_N_REG (CSR_CPI_OCTL_CSR_BASE + 0x73C)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_O_REG (CSR_CPI_OCTL_CSR_BASE + 0x740)
#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_P_REG (CSR_CPI_OCTL_CSR_BASE + 0x744)
#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_CC_REG (CSR_CPI_OCTL_CSR_BASE + 0x748)
#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_DD_REG (CSR_CPI_OCTL_CSR_BASE + 0x74C)
#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_EE_REG (CSR_CPI_OCTL_CSR_BASE + 0x750)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_EN_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x754)
#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_EN_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x758)
#define CSR_CPI_OCTL_CSR_CPI_OCTL_MUL_WR_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x75C)
#define CSR_CPI_OCTL_CSR_CPI_OCTL_CQE_CTL_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x760)

/* CPI_OSCH_CSR Base address of Module's Register */
#define CSR_CPI_OSCH_CSR_BASE (0x43B5000)

/* **************************************************************************** */
/*                      CPI_OSCH_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x0) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x4) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x8) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xC) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x10) /* 单纯 的基于port统计drop数量。对应HVA P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_ERROR_CNT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x14) /* 单纯的基于port统计err数量。对应P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_ERROR_CNT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x18) /* 单纯的基于port统计err数量。对应P类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT0_REG                                                                                                             \
    (CSR_CPI_OSCH_CSR_BASE + 0x20) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是PCIe的P报文。 \
                                    */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x24)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x28)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x2C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x30)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x34)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x38)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x3C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x40)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x44)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x48)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x4C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x50)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x54)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x58)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC01_REG (CSR_CPI_OSCH_CSR_BASE + 0x60)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC23_REG (CSR_CPI_OSCH_CSR_BASE + 0x64)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC45_REG (CSR_CPI_OSCH_CSR_BASE + 0x68)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC67_REG (CSR_CPI_OSCH_CSR_BASE + 0x6C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC89_REG (CSR_CPI_OSCH_CSR_BASE + 0x70)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1011_REG (CSR_CPI_OSCH_CSR_BASE + 0x74)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1213_REG (CSR_CPI_OSCH_CSR_BASE + 0x78)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1415_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C)
#define CSR_CPI_OSCH_CSR_OSCH_CEQE_DROP_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x90)    /* ceqe drop counter统计。 */
#define CSR_CPI_OSCH_CSR_OSCH_CEQE_PI_OVERFLOW_REG (CSR_CPI_OSCH_CSR_BASE + 0x94) /* 有统计信号 */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_OVERFLOW_LOW_REG \
    (CSR_CPI_OSCH_CSR_BASE +                        \
        0x98) /* osch所有的fifo overflow统计信号这个地方使用OR的方式操作overflow告警，不对，需要展开。 */
#define CSR_CPI_OSCH_CSR_OSCH_REQ_TIMEOUT_REG (CSR_CPI_OSCH_CSR_BASE + 0x9C) /* 检测oschoutbound request 超时状态 */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_HIGH_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xA0) /* osch 所有fifo的empty告警信号，中域段 */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_LOW_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xA4) /* osch 所有fifo的empty告警信号，低域段 */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_HIGH_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xA8) /* osch 所有fifo的AFULL告警信号，中域段 */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_LOW_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xAC) /* osch 所有fifo的AFULL告警信号，低域段 */
#define CSR_CPI_OSCH_CSR_OSCH_PAYLOAD_FIFO_CTRL_REG (CSR_CPI_OSCH_CSR_BASE + 0xB0) /* payload fifo的afull反压门限。 */
#define CSR_CPI_OSCH_CSR_OSCH_MSI_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xB4) /* msi_tx fifo的afull反压门限。 */
#define CSR_CPI_OSCH_CSR_OSCH_MSI_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xB8) /* msi_tx fifo的afull反压门限。 */
#define CSR_CPI_OSCH_CSR_OSCH_ATOMIC_TX_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xBC) /* atomic_tx fifo的afull反压门限。 */
#define CSR_CPI_OSCH_CSR_OSCH_ATOMIC_TX_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xC0) /* atomic_tx fifo的afull反压门限。 */
#define CSR_CPI_OSCH_CSR_OSCH_CEQE_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xC4) /* ceqe_tx fifo的afull反压门限。 \
                                                                                     */
#define CSR_CPI_OSCH_CSR_OSCH_CEQE_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xC8) /* ceqe_tx fifo的afull反压门限。 \
                                                                                     */
#define CSR_CPI_OSCH_CSR_OSCH_CPLD_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xD0) /* cpld_tx fifo的afull反压门限。 \
                                                                                     */
#define CSR_CPI_OSCH_CSR_OSCH_CPLD_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xD4) /* cpld_tx fifo的afull反压门限。 \
                                                                                     */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_TOPHIGH_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xD8) /* osch 所有fifo的empty告警信号，最高域段 */
#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_TOPHIGH_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0xDC) /* osch 所有fifo的AFULL告警信号，高域段 */
#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q0_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xF0) /* CPATH Q0FIFO的afull反压门限， \
                                                                                      */
#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q0_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xF4) /* CPATH Q0FIFO的afull反压门限， \
                                                                                      */
#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q1_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x100) /* CPATH Q1FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q1_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x104) /* CPATH Q1FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q2_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x110) /* CPATH Q2FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q2_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x114) /* CPATH Q2FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q0_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x120) /* DPATH Q0FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q0_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x124) /* DPATH Q0FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q1_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x130) /* DPATH Q1FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q1_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x134) /* DPATH Q1FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q2_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x140) /* DPATH Q2FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q2_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x144) /* DPATH Q2FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q3_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x150) /* DPATH Q3FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q3_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x154) /* DPATH Q3FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q4_FIFO_CTRL0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x160) /* DPATH Q4FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q4_FIFO_CTRL1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x164) /* DPATH Q4FIFO的afull反压门限， */
#define CSR_CPI_OSCH_CSR_OSCH_RESERVED0_REG (CSR_CPI_OSCH_CSR_BASE + 0x170)
#define CSR_CPI_OSCH_CSR_OSCH_RESERVED1_REG (CSR_CPI_OSCH_CSR_BASE + 0x174)
#define CSR_CPI_OSCH_CSR_OSCH_RESERVED2_REG (CSR_CPI_OSCH_CSR_BASE + 0x178)
#define CSR_CPI_OSCH_CSR_GLB_POST_HEAD_CREDIT_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x180) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_POST_PAYLOAD_CREDIT_H_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x184) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_POST_PAYLOAD_CREDIT_L_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x188) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_NON_POST_HEAD_CREDIT_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x190) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_NON_POST_PAYLOAD_CREDIT_H_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x194) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_NON_POST_PAYLOAD_CREDIT_L_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x198) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_CPL_HEAD_CREDIT_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x1A0) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_CPL_PAYLOAD_CREDIT_H_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x1A4) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_CPL_PAYLOAD_CREDIT_L_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x1A8) /* 不使用（pcie3.0相关的FC信用信号）。 */
#define CSR_CPI_OSCH_CSR_GLB_OSCH_CEQE_IN_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x1B0) /* 内部capture信号 */
#define CSR_CPI_OSCH_CSR_GLB_OSCH_CEQE_OUT_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x1B4)
#define CSR_CPI_OSCH_CSR_GLB_CEQE_DROP_TAIL_REG (CSR_CPI_OSCH_CSR_BASE + 0x1C0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D4)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D8)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x1DC)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x1E0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F4)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F8)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x1FC)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x200)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x210)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x214)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x218)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x21C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x220)
#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT01_REG (CSR_CPI_OSCH_CSR_BASE + 0x230)
#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT23_REG (CSR_CPI_OSCH_CSR_BASE + 0x234)
#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x238)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_BP_STS_REG (CSR_CPI_OSCH_CSR_BASE + 0x240)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q0_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x250)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q0_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x254)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q1_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x260)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q1_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x264)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q2_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x270)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q2_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x274)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q3_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x280)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q3_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x284)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q4_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x290)
#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q4_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x294)
#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x298)
#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_PERIOD_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A0)
#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A4) /* PCIE的P类型TLP长度统计 */
#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A8)  /* PCIE的P类型TLP长度统计 */
#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x300) /* each port out-bound scheduling weight */
#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x340) /* each port out-bound scheduling weight */
#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x380) /* each port out-bound scheduling weight */
#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3C0) /* each port out-bound scheduling weight */
#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x400) /* each port out-bound scheduling weight */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x304) /* port C-Path Queues' scheduling weight for 2nd read scheduling */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x344) /* port C-Path Queues' scheduling weight for 2nd read scheduling */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x384) /* port C-Path Queues' scheduling weight for 2nd read scheduling */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3C4) /* port C-Path Queues' scheduling weight for 2nd read scheduling */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x404) /* port C-Path Queues' scheduling weight for 2nd read scheduling */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x308) /* port read scheduling weight for different queue. */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x348) /* port read scheduling weight for different queue. */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x388) /* port read scheduling weight for different queue. */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3C8) /* port read scheduling weight for different queue. */
#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x408) /* port read scheduling weight for different queue. */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x30C) /* dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x34C) /* dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x38C) /* dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3CC) /* dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x40C) /* dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x310) /* dpath rd channel  WRR weight inj a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x350) /* dpath rd channel  WRR weight inj a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x390) /* dpath rd channel  WRR weight inj a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3D0) /* dpath rd channel  WRR weight inj a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x410) /* dpath rd channel  WRR weight inj a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x314) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x354) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x394) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3D4) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x414) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x318) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x358) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x398) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3D8) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x418) /* non-dpath rd channel WRR weight in a port */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x320) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x360) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A0) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E0) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x420) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x324) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x364) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A4) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E4) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x424) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x328) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x368) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A8) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E8) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x428) /* wr channel WRR weight in a port \
                                                                                    */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x32C) /* wr cmd 转DOORBELL的信用的反压门限 */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x36C) /* wr cmd 转DOORBELL的信用的反压门限 */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3AC) /* wr cmd 转DOORBELL的信用的反压门限 */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x3EC) /* wr cmd 转DOORBELL的信用的反压门限 */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x42C) /* wr cmd 转DOORBELL的信用的反压门限 */
#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x330) /* doorbell 溢出历史告警。 */
#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x370) /* doorbell 溢出历史告警。 */
#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3B0) /* doorbell 溢出历史告警。 */
#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3F0) /* doorbell 溢出历史告警。 */
#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x430) /* doorbell 溢出历史告警。 */
#define CSR_CPI_OSCH_CSR_OSCH_CTRL_DOORBELL_CNT_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x500) /* 伪装成DMA 写命令发送给CPI_CTRL的doorbell，对齐的统计计数。 */
#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x504) /* 通道0 WR 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x508) /* 通道0 RD 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x50C) /* 通道0 CPL 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x510) /* 通道1 WR 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x514) /* 通道1 RD 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x518) /* 通道1 CPL 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x51C) /* 通道2 WR 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x520) /* 通道2 RD 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x524) /* 通道2 CPL 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x528) /* 通道3 WR 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x52C) /* 通道3 RD 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x530) /* 通道3 CPL 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x534) /* 通道4 WR 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x538) /* 通道4 RD 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x53C)                                         /* 通道4 CPL 命令PCIE信用申请状态 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x540) /* OSCH内MEMORY的ECC注错控制。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x544) /* OSCH内MEMORY的ECC注错控制。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x548) /* OSCH内MEMORY的ECC注错控制。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x54C) /* OSCH内MEMORY的ECC注错控制。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x550) /* OSCH内MEMORY的ECC注错控制。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_5_REG (CSR_CPI_OSCH_CSR_BASE + 0x554) /* OSCH内MEMORY的ECC注错控制。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x558) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \
                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x55C) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \
                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x560) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \
                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x564) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \
                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x568) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \
                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_5_REG (CSR_CPI_OSCH_CSR_BASE + 0x56C) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \
                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x570) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x574) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x578) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x57C) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x580) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_5_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x584) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x588) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x58C) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x590) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x594) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x598) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */
#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_SEL_REG (CSR_CPI_OSCH_CSR_BASE + 0x59C) /* PORT0~4内ECC 错误地址上报选择 */
#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5A0) /* OSCH内FIFO的overflow告警中断上报。 */
#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5A4) /* OSCH内FIFO的overflow告警中断上报。 */
#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5A8) /* OSCH内FIFO的overflow告警中断上报。 */
#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5AC) /* OSCH内FIFO的overflow告警中断开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5B0) /* OSCH内FIFO的overflow告警中断开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5B4)                                         /* OSCH内FIFO的overflow告警中断开关。 */
#define CSR_CPI_OSCH_CSR_OSCH_CRT_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x5B8)   /* OSCH内的可纠错误中断上报 */
#define CSR_CPI_OSCH_CSR_OSCH_UNCRT_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x5BC) /* OSCH内的不可纠错误中断上报 */
#define CSR_CPI_OSCH_CSR_OSCH_CRT_ERR_INT_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C0)   /* OSCH内的可纠错误中断上报开关 */
#define CSR_CPI_OSCH_CSR_OSCH_UNCRT_ERR_INT_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C4) /* OSCH内的不可纠错误中断上报开关 \
                                                                                    */
#define CSR_CPI_OSCH_CSR_OSCH_ACTIVE_EN_CFG_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C8) /* OSCH内的tx_crd_active_en自定义输出 \
                                                                                 */
#define CSR_CPI_OSCH_CSR_OSCH_NL2NIC_OUTSTANDING_BP_CFG_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x5CC) /* OSCH内各port的AAD FIFO的non l2nic outstanding的bp门限 */
#define CSR_CPI_OSCH_CSR_CEQ_CLS_FIFO_ST_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x600) /* cqe cls fifo status_err */
#define CSR_CPI_OSCH_CSR_GLB_CQE_CI_D_CHL_REG (CSR_CPI_OSCH_CSR_BASE + 0x604)    /* CQE_CI_DP_CHL */
#define CSR_CPI_OSCH_CSR_GLB_DMA_SO_RO_REPLACE_REG (CSR_CPI_OSCH_CSR_BASE + 0x608)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_RLS_TAG_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x60C)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_TIMEOUT_REG (CSR_CPI_OSCH_CSR_BASE + 0x610)
#define CSR_CPI_OSCH_CSR_GLB_CP_CQE_CREDIT_PORT_REG (CSR_CPI_OSCH_CSR_BASE + 0x614)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_HI_LMT_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x618)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_HI_LMT_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x61C)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_LO_LMT_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x620)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_LO_LMT_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x624)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_OUT_RANGE_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x628)
#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_OUT_RANGE_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x62C)
#define CSR_CPI_OSCH_CSR_OSCH_PAYLOAD_FIFO1_CTRL_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x630) /* payload fifo1的afull反压门限。(位宽转换FIFO) */
#define CSR_CPI_OSCH_CSR_OSCH_DBELL_FIFO_CTRL_REG (CSR_CPI_OSCH_CSR_BASE + 0x634)   /* doorbell fifo的afull反压门限。 */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_WR_CMD_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x638) /* wr cmd 转DOORBELL的使能信号。 \
                                                                                     */
#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_INITIAL_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x63C)                                           /* wr cmd 转DOORBELL的信用的置位信号 */
#define CSR_CPI_OSCH_CSR_CFG_DPATH_XTS_RD_REG (CSR_CPI_OSCH_CSR_BASE + 0x640) /* 针对XTS对应通道的配置使能 */
#define CSR_CPI_OSCH_CSR_CFG_ROUND_BIT_CHECK_MOD_REG (CSR_CPI_OSCH_CSR_BASE + 0x650) /* ROUND BIT 检查开关。 */
#define CSR_CPI_OSCH_CSR_CFG_PORT1_TO_PORT0_MODE_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x660) /* PORT1 channel到PORT0资源的路由开关。 */
#define CSR_CPI_OSCH_CSR_CFG_NON_L2NIC_LOOP2_EDGE_EN_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x670) /* 在non l2nic inline 数据在第二轮进入Dpath_rd通路时。是否判定F_L边界。 */
#define CSR_CPI_OSCH_CSR_CFG_CUR_CPL_TIMEOUT_DROP_MAX_REG (CSR_CPI_OSCH_CSR_BASE + 0x674)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x700) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x704) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT2_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x708) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT3_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x70C) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT4_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x710) /* 单纯 的基于port统计drop数量。对应HVA NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_ERROR_CNT0_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x714) /* 单纯的基于port统计err数量。对应NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_ERROR_CNT1_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x718) /* 单纯的基于port统计err数量。对应NPCPL类型 */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT0_REG                                                                                                           \
    (CSR_CPI_OSCH_CSR_BASE + 0x720) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是PCIE的NP/CPL报文 \
                                     */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x724)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x728)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x72C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x730)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x734)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x738)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x73C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x740)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x744)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x748)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x74C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x750)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x754)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x758)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x75C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT0_REG                                                                                                           \
    (CSR_CPI_OSCH_CSR_BASE + 0x760) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是HVA端口的的P报文 \
                                     */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x764)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x768)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x76C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x770)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x774)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x778)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x77C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x780)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x784)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x788)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x78C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x790)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x794)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x798)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x79C)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT0_REG                                                                                                            \
    (CSR_CPI_OSCH_CSR_BASE + 0x7A0) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是HVA端口的的NP/CPL报文 \
                                     */
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x7A4)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x7A8)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x7AC)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B4)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B8)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x7BC)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C4)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C8)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x7CC)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D0)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D4)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D8)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x7DC)
#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_COUNT_MODE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7E0)
#define CSR_CPI_OSCH_CSR_OSCH_NPCPL_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7E8) /* PCIE的NPCPL类型TLP长度统计 \
                                                                                         */
#define CSR_CPI_OSCH_CSR_OSCH_NPCPL_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x7EC)  /* PCIE的NPCPL类型TLP长度统计 \
                                                                                         */
#define CSR_CPI_OSCH_CSR_OSCH_HVA_P_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F0) /* HVA的P类型TLP长度统计 */
#define CSR_CPI_OSCH_CSR_OSCH_HVA_P_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F4)  /* HVA的NPCPL类型TLP长度统计 */
#define CSR_CPI_OSCH_CSR_OSCH_HVA_NPCPL_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F8) /* HVA的P类型TLP长度统计 \
                                                                                             */
#define CSR_CPI_OSCH_CSR_OSCH_HVA_NPCPL_PERF_WATCH_TLP_REG \
    (CSR_CPI_OSCH_CSR_BASE + 0x7FC) /* HVA的NPCPL类型TLP长度统计 */

#endif // CPI_REG_OFFSET_H
